Thin-Film Transistor Layering to Prevent Source-Drain Short Circuits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in display technology is the short-circuiting of thin film transistors (TFTs) due to the close proximity of the source and drain, which occurs when the distance between them is reduced to enhance pixel density, leading to defective products.

Innovation Solution

The TFT design includes a first and second conductive pattern with a first intermediate insulating layer in between, allowing the source and drain patterns to be formed through two separate patterning processes, connected via through holes in multiple insulating layers, preventing short-circuiting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the distance between source and drain in TFT is reduced to increase pixel density, then pixel per inch (PPI) is improved, but source and drain are easily short-circuited resulting in defective TFT

Engineering Contradiction:
Improvepixel per inch (PPI)VSAvoidTFT defect rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source and drain patterns are formed through two separate patterning processes with an intermediate insulating layer between them. This segmentation allows independent control of source and drain formation, enabling reduced spacing while preventing short-circuits through the insulating barrier.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A first intermediate insulating layer is introduced between the source pattern and drain pattern. This intermediary layer acts as a physical barrier that prevents direct contact and short-circuiting between source and drain, allowing them to be positioned closer together than previously possible.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If two separate patterning processes are used to form source and drain patterns, then short-circuiting is prevented, but manufacturing complexity increases

Engineering Contradiction:
Improveshort-circuit preventionVSAvoidpatterning process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The formation of source and drain patterns through separate patterning processes is combined with the formation of the intermediate insulating layer in an integrated manufacturing sequence. The intermediate insulating layer is formed between the two patterning steps, merging multiple functions into a coordinated process flow that manages complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly improves TFT product yield by avoiding short-circuiting, enabling a higher pixel per inch (PPI) without defects, and reduces the risk of dark spots in the display apparatus.

Implementation Method 1

an organic hole injection layer and a hole transport layer that sequentially face the anode in this order, thereby the thin film transistor not only can effectively improve the injection capability of holes from the anode

Methodology Applied
Scientific EffectCharge injection and transport: Conduction (electrical)

Implementation Method 2

a gate electrode that controls the source electrode and the drain electrode

Methodology Applied
Scientific EffectElectric field: Electric Field

Data Source

PatentEP3701569B1Thin film transistor, array substrate, fabricating methods thereof, and display apparatus
Publication Date: 2025.10.22 BOE TECHNOLOGY GROUP CO LTD
  • EP3701569B1 patent drawingFigure 1~2-1
  • EP3701569B1 patent drawingFigure 2-2~3-1
  • EP3701569B1 patent drawingFigure 3-2~4-1

AI summary

A thin film transistor may include a gate pattern (11), an active layer pattern (12), a gate insulating layer (13) between the gate pattern (11) and the active layer pattern (12); a first conductive pattern (14) including a first pattern part (141) and a first connecting part (142); a second conductive pattern (15) including a second pattern part (151) and a second connecting part(152); and a first intermediate insulating layer (16) between the first pattern part (141) and the second pattern part (151). The first conductive pattern (14) and the second conductive pattern (15) may be a source pattern and a drain pattern, respectively. A first through hole (161) may be provided on the first intermediate insulating layer (16). The second conductive pattern (15) may be connected to the active layer pattern (12) through the second connecting part (152) in the first through hole (161).