TFT-LCD Array Substrate Sidewall Protection Etching
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Solution Overview
Problem
The existing four-mask process for manufacturing TFT-LCD array substrates is complicated and prone to defects such as metal residue and rough channel surfaces, affecting the electric characteristics of the TFTs, particularly due to multiple-step etching and lateral etching issues.
Innovation Solution
A method involving a substrate with sequentially deposited gate, insulating, and ohmic contact layers, followed by patterning to form gate lines and TFT channels, with a second insulating layer covering the sidewalls and exposing the ohmic contact layer in source and drain regions, and a passivation layer covering the TFT and data lines, while forming a groove over the gate line to prevent cross-talk, simplifying the etching process and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a four-mask process with gray tone mask is used to simplify the manufacturing process, then the manufacturing complexity is reduced, but the etching process becomes more difficult to control causing defects such as metal residue and rough channel surfaces
Solution Approach 1:
The patent segments the etching process into multiple controlled steps: first etching the gate electrode, then etching the active layer, and finally etching the source/drain electrodes. Each step uses specific etching conditions and masks to achieve precise control. This segmentation allows the complex four-mask process to be managed through systematic step-by-step etching operations, reducing defects while maintaining process simplification.
Solution Approach 2:
The patent applies preliminary actions by forming a protective film on the channel region before etching the source/drain electrodes. This protective film prevents lateral etching and metal residue formation during the source/drain electrode etching step. The preliminary protection ensures that when the source/drain electrodes are etched, the channel surface remains smooth and free of defects.
2Manufacturing precision
If multiple-step etching is performed to form the active layer and source/drain electrodes, then the structural precision is improved, but the manufacturing time and process complexity increase
Solution Approach 1:
The patent merges multiple etching operations into an integrated process flow where the gate electrode etching, active layer etching, and source/drain electrode etching are performed in sequence using the same four-mask process framework. By combining these operations with optimized etching conditions and a protective film approach, the patent achieves high structural precision while reducing the overall manufacturing cycle time compared to traditional multi-mask processes.
Solution Approach 2:
The patent maintains continuity of useful action by performing etching operations continuously without unnecessary interruptions. The protective film is formed and then immediately used for the source/drain electrode etching, eliminating idle time. This continuous approach ensures that the multiple-step etching process achieves high precision without excessive manufacturing cycle time extension.
3Area of stationary object
If lateral etching is performed during Mo dry etching to form the source/drain electrodes, then the electrode coverage is improved, but the channel aspect ratio changes and electric characteristics deteriorate
Solution Approach 1:
The patent applies preliminary anti-action by forming a protective film on the channel region before performing the source/drain electrode etching. This protective film counteracts the potential harmful lateral etching effects, preventing the etchant from attacking the channel region. As a result, the channel aspect ratio is maintained and the TFT electric characteristics are preserved while still achieving adequate source/drain electrode coverage.
Solution Approach 2:
The protective film acts as an intermediary layer between the etchant and the channel region during source/drain electrode formation. This intermediary protects the channel from lateral etching damage while allowing the etching process to proceed for source/drain electrode formation. The protective film mediates the conflict between achieving sufficient electrode coverage and maintaining channel integrity, ensuring both requirements are met.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces defects, and improves the yield by minimizing channel residue and short circuits, enhancing the electric characteristics of the TFTs.
Implementation Method 1
a gate insulating layer, an active layer, an ohmic contact layer, and a source/drain metal layer are deposited successively on the gate line and the gate electrode
Implementation Method 2
a gate insulating layer, an active layer, an ohmic contact layer, and a source/drain metal layer are deposited successively on the gate line and the gate electrode
Implementation Method 3
With the second photolithography, a data line, an active region, a source/drain electrode, and TFT channel are formed by source/drain wet etching and multiple-step etching
Implementation Method 4
a data line, an active region, a source/drain electrode, and TFT channel are formed by source/drain wet etching
Implementation Method 5
a data line, an active region, a source/drain electrode, and TFT channel are formed by source/drain wet etching and multiple-step etching (active layer etching→ashing→Mo dry etching→n+etching)
Implementation Method 6
a transparent pixel electrode layer is deposited
Data Source
AI summary
A TFT-LCD array substrate and a method for manufacturing the same are disclosed. In the TFT-LCD array substrate, a first insulating layer, a semiconductor layer, and an ohmic contact layer are formed sequentially on the gate line and the gate electrode, and the ohmic contact layer is formed on the source region and the drain region of the semiconductor layer and exposes the channel; a second insulating layer is formed on the substrate, covers the sidewalls of the gate line and gate electrode, the first insulating layer, the semiconductor layer, and the ohmic contact layer, and exposes the ohmic contact layer in the source region and the drain region; the data line, the source electrode, the pixel electrode, and the drain electrode are formed on the second insulating layer; a passivation layer is formed on the TFT, the gate line, and the data line and exposes the pixel electrode.