TFT LCD Array Substrate 2Mask Gray Tone Process

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Solution Overview

Problem

Conventional TFT LCD array substrate manufacturing processes require multiple masks and photolithography steps, leading to complex processes, low productivity, and inefficient equipment utilization.

Innovation Solution

A 2Mask manufacturing process using gray tone masks and photoresist lifting-off technology to simplify the process, reducing the number of masks and steps to two photolithography processes, allowing for the formation of TFT LCD array substrates with connected gate and data lines through via holes and a shared conductive film.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional multi-mask photolithography processes are used to manufacture TFT LCD array substrates, then manufacturing precision and pattern definition are improved, but device complexity and production cost increase

Engineering Contradiction:
Improvepattern definitionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple photolithography processes into a single integrated process. Specifically, the gate electrode pattern and data line pattern are formed simultaneously in one photolithography step using a dual-layer resist structure, eliminating the need for separate masks and process steps for each pattern, thereby reducing process complexity while maintaining manufacturing precision

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a multi-functional photoresist structure that serves multiple purposes: the first photoresist layer defines the gate electrode pattern, the second photoresist layer defines the data line pattern, and together they form a unified pattern definition system. This universal approach allows one photolithography process to accomplish what traditionally required multiple separate processes

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple masks and photolithography steps are used, then pattern definition quality is improved, but productivity decreases

Engineering Contradiction:
Improvepattern definition qualityVSAvoidequipment productivity
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges multiple sequential photolithography steps into a single parallel process. By forming both gate electrode and data line patterns simultaneously in one exposure and development cycle, the equipment remains productive throughout without idle time between mask changes, thereby improving equipment productivity while maintaining pattern definition quality

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent ensures continuous useful action by eliminating idle time associated with mask changes and process transitions. The dual-layer resist approach allows both patterns to be defined in one continuous exposure process, keeping the photolithography equipment continuously productive without interruption

Inventive Principle:
Principle #20Continuity of useful action

3Device complexity

If the number of masks is reduced to two, then manufacturing cost and process complexity are reduced, but the ability to define multiple patterns separately becomes challenging

Engineering Contradiction:
Improvenumber of masksVSAvoidpattern formation capability
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The patent segments the pattern formation function into two distinct photoresist layers, each responsible for defining a specific pattern. The first photoresist layer is dedicated to gate electrode pattern definition, while the second photoresist layer handles data line pattern definition. This segmentation allows each layer to specialize in one pattern type, maintaining ease of manufacture despite using only two masks

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a vertical dimension to the pattern formation process by using a dual-layer resist structure stacked in the thickness direction. This dimensional approach allows independent pattern definition in each layer while using the same planar mask, effectively solving the pattern formation capability challenge with reduced mask count

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process, reduces production costs, and improves equipment utilization and productivity by eliminating the need for additional masks and steps, while maintaining the quality of the TFT LCD array substrate.

Implementation Method 1

The gray tone mask forms stepwise photoresist with different thicknesses in different regions. The diffraction among the incident light changes transmitting ratio, so the photoresist corresponding to the partially transparent regions of the mask is subject to exposure different from that corresponding to the transparent regions

Methodology Applied
Scientific EffectPhotoresist exposure and development: Photopolymerisation

Implementation Method 2

a second gray tone mask process and a photoresist lifting-off process

Methodology Applied
Scientific EffectChemical dissolution:

Data Source

PatentUS7851806B2Thin film transistor liquid crystal display array substrate and manufacturing method thereof
Publication Date: 2010.12.14 BOE TECHNOLOGY GROUP CO LTD
  • US7851806B2 patent drawing
  • US7851806B2 patent drawing
  • US7851806B2 patent drawing

AI summary

The present invention discloses a method for manufacturing a TFT LCD array substrate by utilizing the gray tone mask technology and the photoresist lifting-off technology with only two masks in two photolithography processes, and to a TFT LCD array substrate manufactured by the same. In the resultant array substrate, the gate line and the data line are perpendicular to and intersect with each other to define the pixel area, and one of the gate line and the data line is continuous and the other is discontinuous. The array substrate is covered with a passivation protection film. The disconnected gate line or the data line is connected together through the via holes formed in the passivation protection film and the connecting conductive film formed on the passivation protection film. The data line and the source electrode and drain electrode of the TFT are made of the same conductive film, and the connecting conductive film and the pixel electrode are made of the same conductive film in the same photolithography process.