TFT-LCD Array Substrate ESD Area Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During the manufacturing of TFT-LCD array substrates, the uneven thickness of resin layers in different areas leads to over-etching issues, particularly in the electrostatic discharge prevention area, causing damage to the data line and reducing product yield.
Innovation Solution
The solution involves forming specific through holes in the gate insulating layer and protection layer, with a passivation layer between transparent electrodes, to ensure consistent thickness and prevent over-etching, using a dry etching method with SF6, O2, and He gases, and incorporating a first transparent electrode that acts as a protective layer during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the protection layer is etched using a uniform process, then the etching is simple to perform, but the uneven thickness of the resin layer causes over-etching in the ESD prevention area and damage to the data line
Solution Approach 1:
The patent applies local quality by forming a first transparent electrode specifically in the ESD prevention area (area b) where the resin layer is thinnest. This local structural modification compensates for the uneven thickness, allowing the etching process to remove the protection layer uniformly without over-etching into the data line in the ESD area, while still achieving complete removal in areas with thicker resin layers.
2Manufacturing precision
If the resin layer thickness is made uniform across all areas, then over-etching is prevented, but the planarization function is compromised and manufacturing complexity increases
Solution Approach 1:
The first transparent electrode acts as an intermediary layer in the ESD prevention area. It is positioned between the protection layer and the data line, providing additional thickness compensation that allows uniform etching parameters to be used across all areas while preventing over-etching damage to the underlying data line structure.
3Productivity
If the etching time is extended to accommodate the thickest areas, then complete etching is achieved, but the data line in the thinnest area is damaged by over-etching
Solution Approach 1:
The first transparent electrode is formed in advance in the ESD prevention area before the protection layer etching process. This preliminary action creates a thickness buffer that prevents over-etching during the etching process, allowing the etching time to be sufficient for complete removal in thick areas without damaging the data line in thin areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent thickness across areas, prevents data line damage, and enhances the manufacturing process by reducing defects and improving yield.
Implementation Method 1
the method further comprises: etching a first through hole in the gate insulating layer, etching a second through hole at a position of the protection layer corresponding to the first through hole
Implementation Method 2
using a dry etching method with SF6, O2, and He gases
Data Source
AI summary
Embodiments of the present invention disclose an array substrate comprising a peripheral wiring area which comprises an electrostatic discharge prevention area. The electrostatic discharge prevention area comprises a substrate (1) on which a gate line(2), a gate insulating layer (3), a data line (4), a protection layer (7) and a transparent electrode (9, 10) are formed. A first through hole (81) is formed in the gate insulating layer (3), a second through hole (82) is formed at the position of the protection layer (7) corresponding to the first through hole (81), and the gate line (2), the data line (4) and the transparent electrode (9, 10) are connected together through the first through hole (81) and the second through hole (82). The present invention also discloses a manufacturing method of the array substrate.