TFT-LCD Driving Circuit Timing Adjustment for Data Confusion

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In TFT-LCD driving circuits, significant time delays in gate driving signals cause data confusion at pixel electrodes, particularly severe in Gate Driver on Array panels due to low electron mobility, leading to incorrect data input and display issues.

Innovation Solution

A TFT-LCD driving circuit with a processing circuit that includes a charge sharing control module and a control signal conversion module, which processes the CPV, OE1, and STV signals to introduce a set time interval between the falling and rising edges of the CLK and CLKB signals, preventing data confusion by staggering these edges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate driving signals are generated without time interval adjustment, then the circuit operation is simple, but data confusion occurs at pixel electrodes due to signal delays

Engineering Contradiction:
Improvedata input accuracyVSAvoidsignal processing circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The processing circuit pre-adjusts the timing of gate driving signals (CLK and CLKB) to create a time interval between their rising and falling edges before they reach the pixel electrodes. This preliminary timing adjustment prevents data confusion by ensuring that data signals are fully written to one row before the next row's gate signal begins, eliminating the need for complex real-time correction mechanisms.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a time interval is introduced between CLK and CLKB signal edges, then data confusion is avoided, but the signal processing complexity increases

Engineering Contradiction:
Improvedisplay accuracyVSAvoidprocessing circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A dedicated processing circuit acts as an intermediary between the signal source and the pixel electrodes. This intermediary circuit receives the original gate driving signals, applies timing adjustments to create the necessary time interval between CLK and CLKB edges, and outputs the corrected signals. This modular approach isolates the complexity within a single processing stage while maintaining clean interfaces with other system components.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces complex mechanical or manual timing adjustment mechanisms with electronic signal processing. By using electronic circuits to automatically generate and adjust the timing of gate driving signals, the system achieves precise time interval control without mechanical components, reducing overall system complexity while improving reliability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If gate driving signals have significant time delays, then the circuit can operate with simpler timing control, but data confusion occurs because data is input to wrong rows

Engineering Contradiction:
Improvesignal processing speedVSAvoiddata row assignment accuracy
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The processing circuit performs preliminary timing adjustment on gate driving signals to create a time interval between CLK and CLKB edges. This ensures that even when signals experience delays during transmission, the data signals will be written to the correct pixel rows without confusion, preserving data integrity while allowing fast signal processing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9224347B2TFT-LCD driving circuit
Publication Date: 2015.12.29 BEIJING BOE OPTOELECTRONCIS TECH CO LTD
  • US9224347B2 patent drawing
  • US9224347B2 patent drawing
  • US9224347B2 patent drawing

AI summary

A TFT-LCD driving circuit is disclosed. The TFT-LCT driving circuit comprises input terminals, output terminals, and a processing circuit connected between the input terminals and the output terminals, for processing a CPV signal, an OE1 signal, an OE2 signal, and a STV signal, so that a set time interval exists between a falling edge of the output CLK signal and a rising edge of the CLKB signal in one cycle of the CLK signal, or that the set time interval exists between a rising edge of the output CLK signal and a falling edge of the CLKB signal in one cycle of the CLKB signal. Confusion of data input to pixel electrodes due to delays of gate driving signals may be avoided by the TFT-LCD driving circuit.