TFT-LCD Array Substrate ITO Gap Reduction via Dry Etching
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Solution Overview
Problem
Current TFT-LCD array substrate manufacturing techniques, such as the 4Mask and 5Mask methods, are unable to reduce the minimum gap in the ITO pattern below 2.25 um, limiting display transmittance and increasing production costs.
Innovation Solution
A method involving sequential deposition and etching processes on a glass substrate, including forming a gate electrode, active layer, source/drain electrodes, passivation layer, and ITO film, with additional dry etch and wet etch steps to reduce ITO electrode gaps to approximately 1.9 um, enhancing transmittance and reducing production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 4Mask or 5Mask techniques are used, then the manufacturing process is simple and well-established, but the minimum gap in ITO pattern cannot be reduced below 2.25 um
Solution Approach 1:
The patent divides the ITO pattern formation into multiple stages: first forming a continuous ITO layer, then using photo resist patterns to define gaps, and finally using selective etching to create the desired gap structure. This segmentation allows precise control of gap sizes below the conventional 2.25 um limit while maintaining manufacturing feasibility.
Solution Approach 2:
The patent applies photo resist coating and exposure before the etching process, creating a preliminary pattern that guides subsequent etching steps. This preliminary action enables precise gap definition by transferring the photo resist pattern into the ITO structure through controlled etching, achieving sub-2.25 um gap precision.
2Illumination intensity
If the ITO pattern gap is reduced to enhance transmittance, then display quality improves, but the etching process fails to break up the ITO pattern at smaller gaps
Solution Approach 1:
The patent applies different etching conditions to different regions of the ITO pattern. By using photo resist protection in specific areas, the etching process selectively removes material only where gaps are desired, while preserving ITO in other regions. This local quality approach enables reliable gap creation at small dimensions without compromising overall pattern integrity.
Solution Approach 2:
The photo resist acts as an intermediary that transfers the desired gap pattern into the ITO structure. The photo resist pattern serves as a template that guides the etching process, enabling precise gap formation at dimensions below 2.25 um while maintaining process reliability through the protective and directional properties of the photo resist layer.
3Illumination intensity
If additional etching steps are added to reduce ITO gaps, then transmittance improves, but production cost increases
Solution Approach 1:
The patent combines the photo resist pattern formation and etching processes into an integrated workflow where the photo resist pattern directly guides the etching process. By merging these steps and using the photo resist as both a protective layer and a pattern template, the process achieves sub-2.25 um gap precision without requiring separate, complex alignment and etching steps, thereby controlling production costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces ITO electrode gaps, thereby improving the transmittance of the TFT-LCD array substrate and lowering production costs by incorporating an additional dry etch process in the ITO electrode formation.
Implementation Method 1
coating a photo resist on the ITO film, and, through exposure and development, removing the photo resist in a TFT area outside the passivation layer via and a part of the photo resist in a pixel area where gaps are to be formed
Implementation Method 2
removing a remaining photo resist in the pixel area where gaps are to be formed from the step b) using a fourth dry etch, so that the ITO film on the gaps to be formed is revealed
Implementation Method 3
removing the ITO film revealed by the steps b) and c) using a third wet etch
Data Source
AI summary
The present invention teaches a TFT-LCD array substrate manufacturing method: a) forming a gate electrode, a gate electrode insulator layer, an active layer, a source electrode and a drain electrode, a passivation layer, and a passivation layer via on top of the drain electrode on a glass substrate; b) depositing an ITO film on the glass substrate processed by the step a), removing through exposure and development the photo resist in a TFT area outside the passivation layer via and a part of the photo resist in a pixel area where gaps are to be formed, and revealing the ITO film outside the passivation layer via in the TFT area; c) removing a remaining photo resist in the pixel area where gaps are to be formed using a fourth dry etch, so that the ITO film on the gaps to be formed is revealed; d) removing the revealed ITO film using a third wet etch; and e) peeling the photo resist not yet removed, and forming an ITO electrode that is connected to the passivation layer via. The present invention also teaches a LCD panel and a LCD device having a TFT-LCD array substrate manufactured by foregoing method.