TFT LCD Pixel Structure Fabrication via Four-Mask Process
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Solution Overview
Problem
The existing methods for fabricating thin film transistor liquid crystal displays require five mask processes, leading to increased manufacturing time and cost, and the use of halftone patterns on photo-masks complicates the design and results in non-uniform patterns.
Innovation Solution
A method is developed to fabricate a pixel structure using four mask processes without halftone techniques, where a transparent conductive layer and a first metallic layer are patterned in the first mask process, followed by the formation of a gate insulating layer and semiconductor layer, then a second metallic layer is patterned, and finally a passivation layer is used to expose the pixel electrode, reducing the number of mask processes and avoiding halftone-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If five mask processes are used to fabricate thin film transistor liquid crystal display, then the manufacturing precision and reliability are maintained, but the manufacturing time and cost increase
Solution Approach 1:
The patent combines the gate electrode pattern and pixel electrode pattern into a single first mask process step. By forming both patterns simultaneously through one photolithography exposure, the number of mask processes is reduced from five to four, directly decreasing manufacturing time while maintaining pattern uniformity through conventional photolithography without halftone techniques
Solution Approach 2:
The patent performs preliminary patterning of both gate and pixel electrode patterns in the first mask process before subsequent layer formation. This preliminary action establishes the electrode structures early in the fabrication sequence, allowing subsequent layers (gate insulating layer, semiconductor layer, etc.) to be formed over these established patterns, thereby reducing the total number of required mask processes
2Productivity
If halftone pattern design is used on photo-mask to reduce mask processes, then the number of mask processes decreases, but the design complexity and pattern uniformity deteriorate
Solution Approach 1:
The patent extracts and eliminates the halftone pattern technique from the fabrication process. By using conventional binary photolithography masks instead of halftone masks, the design complexity is removed while still achieving the goal of reducing mask processes through the merged first mask process that patterns both gate and pixel electrodes simultaneously
Solution Approach 2:
Instead of using halftone patterns to reduce mask steps, the patent inverts the approach by using a single conventional photolithography step to accomplish what would traditionally require multiple steps. The first mask process simultaneously defines both gate electrode and pixel electrode patterns, achieving process reduction through consolidation rather than through halftone complexity
3Productivity
If halftone pattern is used on photo-mask, then the number of mask processes is reduced, but the photoresist pattern uniformity and yield deteriorate
Solution Approach 1:
The patent adopts conventional photolithography masks that can be easily manufactured and replaced, eliminating the need for complex halftone masks. This approach prioritizes manufacturing efficiency through simpler, more reliable masking techniques while maintaining the benefit of reduced total process steps through the merged first mask process
Data Source
AI summary
A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.


