Thin Film Transistor LDD Layer Configuration for Current Reduction
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Solution Overview
Problem
Thin film transistors in display devices, particularly those with LDD layers, experience increased OFF current and optical leak current due to impurity concentration issues and backlight interference.
Innovation Solution
The design includes a semiconductor layer with a channel region, high-concentration impurity layers, and low-concentration impurity layers (LDD) that are strategically positioned and connected via contact holes, with the electrodes spaced apart from the gate electrode to reduce electric field concentration and optical leak current, using polysilicon or microcrystalline silicon materials and specific ion implantation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDD layers are formed to alleviate electric field concentration, then the thin film transistor structure is improved, but OFF current increases due to impurity concentration decrease
Solution Approach 1:
The patent applies local quality by creating distinct regions with different impurity concentrations: high-concentration impurity regions near electrodes for good contact, low-concentration LDD regions for electric field alleviation, and intrinsic/channel regions for proper transistor operation. This spatial differentiation of impurity concentrations optimizes both electrical contact and field distribution while controlling OFF current.
Solution Approach 2:
The patent changes the impurity concentration parameter across different regions of the semiconductor layer. By controlling impurity concentration to be high near electrodes, low in LDD regions, and intrinsic or low in channel regions, the patent achieves proper balance between contact resistance, electric field distribution, and OFF current characteristics.
2Reliability
If LDD layers are formed above the gate electrode, then electric field concentration is alleviated, but optical leak current is generated due to backlight radiation
Solution Approach 1:
The patent applies local quality by forming LDD layers only in specific regions that do not overlap with the gate electrode projection, while still providing electric field alleviation at critical locations near the electrodes. This spatial selective formation eliminates optical leak current paths while maintaining electrical field management benefits.
3Area of stationary object
If electrodes are positioned closer to the gate electrode, then device area is reduced, but electric field concentration increases
Solution Approach 1:
The patent introduces LDD layers as intermediary regions between the high-potential electrodes and the gate electrode. These LDD layers act as buffer zones that reduce electric field concentration at the electrode-gate interface, allowing electrodes to be positioned closer to the gate without suffering from excessive field concentration effects.
Solution Approach 2:
The patent changes the impurity concentration parameter in the regions between electrodes and gate electrode, creating low-concentration LDD regions that modify the electric field distribution. This parameter change allows closer electrode positioning while maintaining acceptable electric field levels through the graded concentration profile.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces OFF current and optical leak current in thin film transistors, improving the performance and efficiency of display devices by minimizing electric field effects and light interference.
Implementation Method 1
specific ion implantation techniques
Data Source
AI summary
A display device which has thin film transistors, wherein a semiconductor layer includes a first layer, second layers and third layers, the first layer has a channel region, the second layers are an impurity layer, the third layers are a low-concentration impurity layer, the second layers have connection portions connected with an electrodes, the third layers are formed to annularly surround the second layers, a channel-region-side edge portion out of edge portions of the third layer is in contact with the first layer, the edge portions of the third layer but the channel-region-side edge portion are in contact with an interlayer insulation film, the second layers have a first region where the second layer overlaps with a gate electrode and a second region where the second layer does not overlap with the gate electrode, and the connection portion is in the second region.