TFT Array Panel Light Shielding and Single-Mask Manufacturing
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Solution Overview
Problem
Thin film transistor (TFT) array panels in liquid crystal displays (LCDs) face issues with leakage current, particularly when the semiconductor layer is exposed to light, leading to increased photoelectron generation and manufacturing complexity due to multiple photolithography processes.
Innovation Solution
The TFT array panel design incorporates a semiconductor with a protruding portion extending below the drain electrode, positioned within the gate line's occupying area, and a pixel electrode that contacts both the drain electrode and semiconductor, with the protruding portion blocked by the gate line to prevent light penetration, and a method using one mask to form the semiconductor stripe and data metal layers, reducing the number of photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the semiconductor layer is exposed to light, then photoelectron generation increases improving the light sensitivity, but leakage current increases deteriorating the device reliability
Solution Approach 1:
The semiconductor layer is divided into a light-exposed region (for photoelectron generation) and a light-shielded region (for low leakage current). The gate line structure creates a spatial segmentation where the gate electrode area shields the semiconductor while non-gate areas remain exposed to light, resolving the contradiction between light sensitivity and leakage current.
Solution Approach 2:
Different regions of the semiconductor layer have different light exposure characteristics. The region under the gate line has different properties (light-shielded, low leakage) compared to the region outside the gate line (light-exposed, high photoelectron generation). This local differentiation allows the device to simultaneously achieve both light sensitivity and low leakage current.
2Manufacturing precision
If multiple photolithography processes are used to manufacture the TFT array panel, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
Multiple photolithography processes are merged into a single process by designing the mask pattern to simultaneously define the gate line, gate electrode, and semiconductor layer regions. The gate line structure serves multiple functions: as an electrical conductor, as a light-shielding mask, and as a structural element that defines the semiconductor region, thereby reducing the total number of photolithography steps required.
Solution Approach 2:
The gate line structure is designed to serve multiple functions simultaneously: it acts as the electrical gate electrode, as a photolithography mask for defining the semiconductor region, and as a light-shielding element to prevent leakage current. This multi-functionality reduces the need for separate structures and processes, simplifying manufacturing while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces leakage current by blocking light and simplifies the manufacturing process, enhancing the reliability and display quality of LCDs by minimizing exposure of the semiconductor to light and reducing the complexity and cost of production.
Implementation Method 1
the protruding portion blocked from light penetrating the insulation substrate by the gate line including the gate electrode
Data Source
AI summary
A thin film transistor (“TFT”) array panel is provided. The TFT array panel includes an insulation substrate, a gate line formed on the insulation substrate and including a gate electrode, a data line insulated from and intersecting the gate line, and including a source electrode, a drain electrode opposite to the source electrode on the gate line, and a semiconductor formed in a layer between the data line and the gate line, and having a protruding portion extending below the drain electrode, wherein a portion of the semiconductor extending towards the drain electrode, from an area occupied by the data line, is positioned within an occupying area of the gate line including the gate electrode.