Thin Film Transistor with Lightly Doped Region for Leakage Current Reduction
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Solution Overview
Problem
Thin film transistors in liquid crystal displays experience significant leakage current, leading to display gray scale deviations and increased energy consumption, which existing manufacturing methods fail to adequately address.
Innovation Solution
A manufacturing method for thin film transistors that includes forming an active layer with a source ohmic contact region, a drain ohmic contact region, a channel region, and a lightly doped region between the drain and channel, reducing leakage current by concentrating hot carriers near the drain and increasing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional thin film transistor structure is used, then manufacturing process is simple, but leakage current is too large causing display gray scale deviation and increased energy consumption
Solution Approach 1:
The active layer is segmented into multiple functional regions: source ohmic contact region, drain ohmic contact region, channel region, and lightly doped region. This segmentation allows each region to perform its specific function optimally, with the lightly doped region specifically designed to reduce leakage current while maintaining overall manufacturing feasibility
Solution Approach 2:
Different regions of the active layer are assigned different doping concentrations and properties: the source and drain regions have high doping for ohmic contact, the channel region has appropriate doping for carrier transport, and the lightly doped region has low doping to reduce leakage. This local differentiation of properties enables the transistor to achieve low leakage current without completely redesigning the entire device structure
2Reliability
If lightly doped region is added to active layer, then leakage current decreases and on-state current increases, but manufacturing process complexity increases
Solution Approach 1:
The lightly doped region is formed during the active layer fabrication process itself, before subsequent transistor structure formation. This preliminary action integrates the leakage reduction feature into the base manufacturing flow rather than requiring separate additional processing steps, thereby improving reliability without proportionally increasing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively decreases leakage current, enhances the on-state current, and improves the overall performance of the thin film transistor, resulting in better comprehensive performance and reduced energy consumption.
Implementation Method 1
increasing carrier mobility
Implementation Method 2
concentrating hot carriers near the drain
Data Source
Figure 1~2
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AI summary
Embodiments of the present invention provide a thin film transistor and a manufacturing method thereof, an array substrate including the thin film transistor, and a manufacturing method of the array substrate, relate to the field of the display technology and can reduce the leakage current of the thin film transistor. The thin film transistor comprises an active layer, a gate insulation layer, a gate, an interlayer insulation layer, a source and a drain formed on a base substrate, the interlayer insulation layer and the gate insulation layer are provided therein with through holes corresponding to the source and the drain; the active layer comprises a source ohmic contact region connected with the source, a drain ohmic contact region connected with the drain, a channel region serving as a channel located below the gate, and a lightly doped region between the drain ohmic contact region and the channel region, or the active layer comprises a source ohmic contact region connected with the source, a drain ohmic contact region connected with the drain, a channel region serving as a channel located below the gate, and two lightly doped regions located between the drain ohmic contact region and the channel region and between the source ohmic contact region and the channel region respectively.