TFT Array Substrate Semi-Transmissive Mask Edge Thinning
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Solution Overview
Problem
The 4M process for TFT array substrate manufacturing faces issues with residual amorphous silicon and heavily doped silicon at the second metal edge, affecting optical stability, electrical performance, aperture ratio, power consumption, and reliability due to the use of halftone or gray-tone mask patterning.
Innovation Solution
A manufacturing method that involves using a semi-transmissive mask with a reduced thickness edge portion for the photoresist layer, allowing for easier etching of the semiconductor layer at the metal wire structure edges, thereby reducing the problem of tailing and improving the TFT's optical and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a halftone mask or gray-tone mask patterning process is used in the 4M process, then the production capacity is increased and cost is reduced compared to 5M process, but residual amorphous silicon and heavily doped silicon remain at the second metal edge, affecting TFT optical stability, electrical performance, aperture ratio, power consumption and reliability
Solution Approach 1:
The patent applies local quality by creating a variable thickness photoresist layer where the edge portion has a different (thinner) thickness than the center portion. This local differentiation allows the edge regions to be etched more effectively while maintaining the benefits of the 4M process, thus resolving the contradiction between productivity improvement and reliability maintenance.
2Ease of manufacture
If a halftone mask or gray-tone mask patterning process is used, then the manufacturing process is simplified to 4M, but the metal wire structure edge becomes coarse with residual silicon, reducing aperture ratio and increasing power consumption
Solution Approach 1:
The patent creates a photoresist layer with non-uniform thickness where edge portions are thinner than center portions. This local quality variation enables precise edge definition during etching while maintaining the simplified 4M manufacturing process, thereby resolving the contradiction between ease of manufacture and manufacturing precision.
3Device complexity
If the photoresist layer has uniform thickness, then the manufacturing process is simpler, but the semiconductor layer at the edge of metal wiring structure is difficult to etch completely, causing tailing of the active layer
Solution Approach 1:
The patent implements a photoresist layer with different thicknesses at different locations - thinner at edges and thicker at the center. This local quality approach allows complete etching of the semiconductor layer at metal wire edges while maintaining structural integrity elsewhere, resolving the contradiction between device complexity and manufacturing precision.
Solution Approach 2:
The patent performs preliminary action by pre-thinning the edge portions of the photoresist layer before the etching process. This preliminary modification of the photoresist layer structure enables better etching control and prevents active layer tailing, thereby resolving the contradiction between device complexity and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the optical stability, electrical performance, aperture ratio, reliability, and power consumption of the TFT array substrate by ensuring a finer metal wire structure and reducing residual silicon issues, leading to improved overall performance.
Implementation Method 1
exposing and developing the photoresist material by using the semi-transmissive mask to obtain a photoresist layer
Implementation Method 2
performing ashing treatment on the photoresist layer to reduce the thickness of the photoresist layer such that the groove is converted to a through hole which exposes an upper surface of the metal wire structure
Implementation Method 3
performing a first wet etching, forming a metal wire structure from the source/drain metal layer
Implementation Method 4
performing a first dry etching, forming an active layer structure from the semiconductor layer
Data Source
AI summary
The invention provides a manufacturing method of the TFT array substrate. Compared to existing 4M process, the invention changes the structural design of the semi-transmissive mask for the photoresist layer for patterning the source/drain metal layer and the semiconductor layer. The edge forms a reduced thickness edge portion, so that the edge of the photoresist layer is thinned, and thereby the width of the photoresist layer is easily reduced in subsequent processes, and the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the tailing problem of the active layer at edges of source/drain to achieve finer metal wire structure, and improve optical stability, electrical performance, aperture ratio, reliability, power consumption, and the overall performance of the TFT array substrate. The residual problem of amorphous and heavily doped silicon on source/drain edge in original process is solved or reduced.