Self-Aligned TFT Memory Cell Shared Electrode Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory cells based on thin-film transistors (TFTs) in memory arrays suffer from misalignment issues between the TFT and the capacitor, leading to increased capacitance and performance degradation due to leakage caused by normal silicon transistors used as selectors.
Innovation Solution
A memory cell design featuring a TFT and a capacitor with a shared contact electrode, where the capacitor is formed first and under the TFT to reduce capacitance variation, and the TFT and capacitor are self-aligned, utilizing a vertical architecture to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If normal silicon transistors are used as selectors in memory cells, then high-speed performance is achieved, but leakage occurs causing charge retention problems
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional silicon to thin-film transistor technology. TFTs exhibit different electrical characteristics including lower leakage current while maintaining adequate switching speed, thus resolving the contradiction between speed and leakage by transitioning to a different material regime with optimized parameters for memory application
Solution Approach 2:
The invention employs composite material structures in the TFT construction, including multiple dielectric layers (gate dielectric, capacitor dielectric), conductive layers (gate electrode, source/drain electrodes), and semiconductor layers. This composite approach enables simultaneous optimization of switching performance and leakage characteristics through carefully selected material combinations
2Ease of manufacture
If TFT and capacitor are separately aligned, then manufacturing flexibility is maintained, but misalignment occurs increasing capacitance variation
Solution Approach 1:
The patent merges the TFT and capacitor structures by forming the capacitor within the TFT device area. The gate electrode of the TFT serves as one plate of the capacitor, and the channel layer or adjacent dielectric forms the other plate. This integration eliminates separate alignment requirements between TFT and capacitor, resolving the contradiction by making the structures interdependent rather than independent
Solution Approach 2:
The capacitor is nested within the TFT structure, with the capacitor plates formed using the same electrode and dielectric layers as the TFT. The capacitor occupies the space between the gate electrode and channel layer, effectively nesting one functional element within another. This nesting approach eliminates misalignment issues while maintaining compact design
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.