Thin Film Transistor Metal Induction Crystallization

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Solution Overview

Problem

Low-temperature polysilicon thin film transistors (LTPS-TFTs) used in liquid crystal displays have high impurity content, leading to significant leakage current and poor switching characteristics, which hinders their application in high-definition TFT-LCDs and current-driven TFT-OLEDs.

Innovation Solution

The method involves forming an active layer in thin film transistors using atomic layer deposition (ALD) to deposit an inducing metal on an amorphous silicon layer, followed by heat treatment for metal induction crystallization and lateral crystallization, reducing impurity content and improving transistor performance at low temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LTPS-TFT technology is used to achieve higher mobility and better stability, then drive capacity and device performance are improved, but impurity content in the active layer increases leading to greater leakage current

Engineering Contradiction:
Improvetransistor stability and drive capacityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes metal impurities from the active layer through selective etching processes. The method involves treating the active layer with a first etchant to remove metal particles, then treating with a second etchant to further purify the layer, thereby reducing leakage current while maintaining the benefits of LTPS-TFT technology

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies preliminary protective measures by forming a protective film on the active layer before metal particle removal treatment. This protective film prevents damage to the active layer during the etching process, ensuring that the purification process does not compromise the transistor's performance or structure

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If amorphous silicon thin film field effect transistors are used, then manufacturing process is mature and easy to implement, but mobility is low and device size is large

Engineering Contradiction:
Improveprocess maturityVSAvoidcarrier mobility
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent changes the material parameter of the active layer from amorphous silicon to LTPS (low-temperature polysilicon). This parameter change increases carrier mobility by hundreds of times compared to amorphous silicon, enabling high-definition TFT-LCDs and current-driven TFT-OLEDs while maintaining low processing temperatures

Inventive Principle:
Principle #35Parameter changes

3Productivity

If LTPS-TFT is used to reduce device size and improve drive capacity, then integration of peripheral circuits is enabled, but impurity content increases affecting switching characteristics

Engineering Contradiction:
Improvedrive capacity and integration capabilityVSAvoidswitching characteristics
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent extracts metal impurities from the active layer through a two-stage etching process. The first etchant removes bulk metal particles, while the second etchant removes remaining metal contaminants, thereby purifying the active layer and restoring proper switching characteristics while maintaining high drive capacity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a feedback mechanism by using metal particle removal treatment to eliminate impurities that degrade performance. The process continuously improves the active layer quality by removing contaminants, ensuring that switching characteristics meet required specifications for high-definition display applications

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces impurity content and enhances the switching characteristics of thin film transistors, enabling their use in high-definition displays with improved mobility and stability, while maintaining low processing temperatures.

Implementation Method 1

depositing an inducing metal on an amorphous silicon layer of the source and drain regions by an atomic layer deposition (ALD) method

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

conducting heat treatment on the amorphous silicon layer deposited with the inducing metal so that metal induction crystallization and metal induction lateral crystallization take place in the amorphous silicon layer

Methodology Applied
Scientific EffectMetal induction crystallization: Crystallisation

Implementation Method 3

conducting heat treatment on the amorphous silicon layer deposited with the inducing metal

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Data Source

PatentUS9040988B2Thin film transistor and manufacturing method thereof, and array substrate
Publication Date: 2015.05.26 BOE TECHNOLOGY GROUP CO LTD
  • US9040988B2 patent drawing
  • US9040988B2 patent drawing
  • US9040988B2 patent drawing

AI summary

The disclosure discloses a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which can manufacture a thin film transistor with lower contents of impurity at a low temperature. The thin film transistor comprises: a substrate, and an active layer disposed on the substrate, the active layer comprising a source region, a drain region and a channel region, wherein the active layer is formed by depositing an inducing metal on an amorphous silicon layer on the substrate by an atomic layer deposition (ALD) method and then conducting heat treatment on the amorphous silicon layer deposited with the inducing metal so that metal induction crystallization and metal induction lateral crystallization take place in the amorphous silicon layer.