Thin-Film Transistor Substrate With Metal Oxide Drain Electrode
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Solution Overview
Problem
The distance between the source and drain electrodes in thin-film transistors is limited by photolithography resolution, hindering the reduction of pixel size and aperture ratio in liquid-crystal displays, which is essential for improving display resolution.
Innovation Solution
A thin-film transistor substrate design that includes a substrate with a gate electrode, gate insulating layer, active layer with metal oxide, source electrode, first insulating layer, and a drain electrode with a metal oxide layer, where the distance between the source and drain electrodes can be reduced from 2 μm to 10 μm, allowing for a smaller active layer width and improved aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the distance between source and drain electrodes is reduced to improve pixel resolution, then the aperture ratio is reduced significantly
Solution Approach 1:
The patent introduces a vertical stacking dimension by placing the pixel electrode above the liquid crystal layer rather than in the same plane as the source and drain electrodes. This three-dimensional arrangement allows the source and drain electrodes to be positioned closer together horizontally without further reducing the aperture area, as the pixel electrode is separated in the vertical dimension.
Solution Approach 2:
The patent implements a nested structure where the pixel electrode is positioned within the vertical space above the liquid crystal layer, which itself is between the thin-film transistor substrate and color filter substrate. This nesting allows multiple functional layers to occupy different vertical levels, enabling closer source-drain spacing while preserving aperture ratio.
2Measurement precision
If the size of each pixel is reduced to improve resolution, then the aperture ratio is reduced significantly
Solution Approach 1:
By moving the pixel electrode to a higher vertical level above the liquid crystal layer, the patent creates additional spatial freedom in the horizontal plane. This allows pixel dimensions to be reduced for higher resolution without proportionally reducing the aperture area, as the electrode occupies vertical rather than horizontal space.
Solution Approach 2:
The patent creates a dynamic spatial arrangement where electrodes and functional layers are positioned at different vertical levels rather than fixed in a single plane. This dynamic three-dimensional configuration allows flexible optimization of both pixel size and aperture ratio that would not be possible with traditional planar structures.
3Manufacturing precision
If photolithography resolution limits are used to determine electrode spacing, then manufacturing precision is maintained but device complexity increases
Solution Approach 1:
The patent resolves the photolithography limitation by transitioning from two-dimensional planar electrode arrangement to three-dimensional vertical stacking. This allows source and drain electrodes to be positioned closer together using standard photolithography processes, while the pixel electrode is formed at a different vertical level, effectively bypassing the resolution limit without requiring more complex lithography techniques.
Data Source
AI summary
An embodiment of the invention provides a thin-film transistor substrate, including: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the substrate and covering the gate electrode; an active layer disposed on the gate insulating layer and above the gate electrode, wherein the active layer includes a metal oxide; a source electrode disposed on and electrically connecting to the active layer; a first insulating layer covering the source electrode; and a drain electrode disposed on and electrically connecting to the active layer, wherein the drain electrode includes a metal oxide layer.