Thin Film Transistors With Multi-Layer Channel Structure
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Solution Overview
Problem
Commercially produced liquid crystal display apparatuses using amorphous silicon thin film transistors have low charge mobility, limiting operational speed and being susceptible to degradation due to plasma exposure.
Innovation Solution
A thin film transistor with a double-layer channel structure, where the upper layer is doped with a carrier acceptor such as Cu, Ag, or N, and formed using a ZnO-based material, to enhance charge mobility and resist plasma-induced degradation, with the upper layer having a carrier concentration lower than the lower layer and a thickness of 10-100 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as the channel layer material, then the manufacturing process is simple and well-established, but the charge mobility is very low (approximately 0.5 cm2/Vs)
Solution Approach 1:
The patent uses a composite channel layer structure consisting of a lower amorphous silicon layer and an upper crystalline semiconductor layer. This composite structure combines the manufacturing advantages of amorphous silicon with the high charge mobility of crystalline materials, achieving charge mobility greater than 10 cm2/Vs while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The channel layer is segmented into two distinct layers with different materials and properties: a lower amorphous silicon layer that provides ease of manufacture and a upper crystalline semiconductor layer that provides high charge mobility. This segmentation allows each layer to contribute its optimal characteristics to the overall device performance
2Device complexity
If amorphous silicon channel layer is used, then the device structure is simple, but the operational speed is limited due to low charge mobility
Solution Approach 1:
By combining amorphous silicon with crystalline semiconductor materials in a layered composite structure, the patent achieves high charge mobility (>10 cm2/Vs) that enables fast operational speed, while maintaining a relatively simple overall device structure that is compatible with existing manufacturing processes
3Ease of manufacture
If the channel layer is exposed to plasma for manufacturing processes, then the manufacturing steps can be completed, but the channel layer characteristics degrade
Solution Approach 1:
The upper crystalline semiconductor layer is formed first, before the lower amorphous silicon layer is deposited. This preliminary action protects the high-mobility crystalline layer from subsequent plasma exposure during the formation of other device components, preventing characteristic degradation while allowing manufacturing processes to proceed
Solution Approach 2:
The lower amorphous silicon layer acts as an intermediary protective layer that shields the upper crystalline semiconductor layer from plasma exposure during subsequent manufacturing processes. This intermediary structure allows plasma-based manufacturing steps to be completed without degrading the sensitive crystalline channel layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly increases charge mobility and prevents degradation of the channel layer due to plasma exposure, enabling faster operational speeds and improved reliability in liquid crystal display apparatuses.
Implementation Method 1
The upper layer may be doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer
Implementation Method 2
the upper layer may be formed using a sputtering method with a target doped with the carrier acceptor
Data Source
AI summary
A transistor may include: a gate insulting layer, a gate electrode formed on a bottom side of the gate insulating layer, a channel layer formed on a top side of the gate insulating layer, a source electrode that contacts a first portion of the channel layer, and a drain electrode that contacts a second portion of the channel layer. The channel layer may have a double-layer structure, including an upper layer and a lower layer. The upper layer may have a carrier concentration lower than that of the lower layer. The upper layer may be doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer.