Thin Film Transistor With Nested Ring Electrodes
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Solution Overview
Problem
In display devices, the stability of current output from Thin Film Transistors (TFTs) is affected by fluctuations in the width-to-length ratio of the channel, leading to reduced pixel aperture ratios and increased luminance requirements, which shorten the lifetime of luminescent materials.
Innovation Solution
A thin film transistor design featuring double active layers with ring-shaped drains and sources, connected through conductive patterns and insulation layers, maintains a stable channel width-to-length ratio, reducing current fluctuations and improving aperture ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the TFT channel length is reduced to improve aperture ratio, then the aperture ratio increases, but the width-to-length ratio fluctuates causing current instability
Solution Approach 1:
The patent implements a nested structure where the first drain electrode is positioned inside the second drain electrode, and the first source electrode is positioned inside the second source electrode. This nested configuration allows the TFT to maintain a stable effective channel width-to-length ratio while reducing the overall device footprint, thereby improving aperture ratio without sacrificing current stability.
Solution Approach 2:
The patent transitions from a conventional planar TFT structure to a multi-layer stacked structure with first and second active layers arranged in different planes. This dimensional change allows the channel to extend through multiple layers, effectively increasing the channel length without increasing the planar footprint, thus maintaining current stability while improving aperture ratio.
2Illumination intensity
If the aperture ratio is increased to improve luminance, then the luminance increases, but the TFT dimension increases reducing manufacturing efficiency
Solution Approach 1:
The nested electrode configuration allows the TFT to achieve larger effective aperture area by utilizing vertical stacking rather than horizontal expansion. The first drain inside the second drain and first source inside the second source create a compact structure that maximizes light-emitting area without proportionally increasing the overall device area, thereby improving manufacturing efficiency.
Solution Approach 2:
By arranging active layers and electrodes in multiple vertical layers rather than expanding horizontally, the patent increases the effective aperture area in the vertical dimension. This allows higher luminance output without increasing the planar footprint, maintaining high manufacturing efficiency.
3Area of stationary object
If the TFT is miniaturized to improve aperture ratio, then the aperture ratio improves, but the current output stability decreases
Solution Approach 1:
The nested electrode structure maintains a stable effective channel geometry by having the inner electrodes (first drain and source) positioned within the outer electrodes (second drain and source). This configuration ensures that the effective channel width-to-length ratio remains stable even when the overall device is miniaturized, preserving current output stability while improving aperture ratio.
Solution Approach 2:
The multi-layer stacked structure allows the channel to extend through multiple vertical layers, maintaining a stable effective channel length that is decoupled from the planar device dimensions. This enables miniaturization in the planar direction while preserving current stability through the vertical channel extension.
Data Source
AI summary
The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.