TFT Array Substrate Node Contact Hole Design
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Solution Overview
Problem
Current display technologies face challenges in achieving an efficient space layout and connection structure between thin-film transistors (TFTs), capacitors, and wirings, particularly in compact and high-resolution displays, where a more efficient connection is needed to enhance performance and resolution.
Innovation Solution
A thin-film transistor (TFT) array substrate is designed with a specific configuration including a first and second conductive layer, node contact holes, and connection nodes, where the connection part between the contact holes has a width smaller than the individual holes, and is formed using a method that involves forming conductive layers and insulating layers with precise etching to create a connection node that electrically connects the layers, optimizing the layout and reducing design margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional connection structures are used between conductive layers, then manufacturing is simpler, but space layout efficiency deteriorates and design margins increase
Solution Approach 1:
The node contact hole is segmented into three distinct parts: a first contact hole part exposing the first conductive layer, a second contact hole part exposing the second conductive layer, and a connection part connecting them. This segmentation allows each part to be optimized independently for space efficiency while maintaining manufacturing feasibility.
Solution Approach 2:
The connection structure transitions from a conventional planar contact hole to a multi-dimensional structure with varying widths. The connection part has a width smaller than both the first and second contact hole parts, creating a tapered or necked geometry that optimizes space utilization in the vertical dimension while improving lateral space layout efficiency.
2Manufacturing precision
If larger contact hole widths are used, then manufacturing is easier, but short malfunctions may occur and resolution decreases
Solution Approach 1:
Different parts of the node contact hole have different widths optimized for different functions. The first and second contact hole parts have larger widths for easier manufacturing and better electrical contact, while the connection part has a smaller width to prevent short malfunctions between adjacent conductive elements. This local quality variation achieves both manufacturing precision and reliability.
3Productivity
If design margins are reduced for compact layout, then resolution improves, but manufacturing precision requirements increase
Solution Approach 1:
The node contact hole structure employs dynamic width variation along its depth, with the connection part having a smaller width than the upper and lower contact hole parts. This dynamic geometry allows the structure to maintain adequate manufacturing margins at the wider ends while achieving compact dimensions at the connection region, thereby improving display resolution without excessively increasing manufacturing precision requirements.
Data Source
AI summary
A thin-film transistor (TFT) array substrate includes: a TFT including an active layer, a gate electrode, a source electrode, and a drain electrode; a first conductive layer disposed in a same layer as one of the active layer, the gate electrode, the source electrode, and the drain electrode; a second conductive layer disposed in a different layer from the first conductive layer; a node contact hole including a first contact hole part which exposes the first conductive layer, a second contact hole part which exposes the second conductive layer, and a connection part which connects the first contact hole part and the second contact hole part and has a width smaller than that of the first contact hole part and that of the second contact hole part; and a connection node disposed in the node contact hole to electrically connect the first and second conductive layers.