Thin Film Transistor Non-Overlapping Electrodes Parasitic Capacitance
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Solution Overview
Problem
Existing thin film transistors face challenges in miniaturization due to parasitic capacitance caused by overlapping regions between gate and source/drain electrodes, which affects their operating characteristics and hinders size reduction.
Innovation Solution
A thin film transistor design where the source and drain electrodes are in the same layer, directly contacting the active layer, with a gate electrode positioned such that its orthographic projections do not overlap with these electrodes, and a conductorization process is applied to regions of the active layer not covered by the electrodes, avoiding parasitic capacitance while allowing for miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode overlaps with source and drain electrodes in the conventional structure, then the transistor can be fabricated with standard processes, but parasitic capacitance is generated between the gate and source/drain electrodes which degrades device performance and limits miniaturization
Solution Approach 1:
The patent transitions from a planar overlapping structure to a three-dimensional stacked structure where the gate electrode is positioned above the active layer, and source/drain electrodes are positioned at the same layer. This dimensional separation eliminates parasitic capacitance between gate and source/drain electrodes while maintaining effective gate control over the active layer through vertical stacking.
Solution Approach 2:
The patent segments the electrode structures into distinct layers: the active layer forms a base, the gate electrode is positioned above the active layer, and source/drain electrodes are positioned at the same layer as the active layer. This segmentation separates the gate control function from the source/drain transport function, eliminating harmful electromagnetic coupling while preserving electrical functionality.
2Ease of operation
If via holes are introduced to connect electrodes across layers, then electrical connection can be achieved, but the device structure becomes more complex and fabrication difficulty increases
Solution Approach 1:
The patent merges the source/drain electrodes with the active layer by positioning them at the same layer, creating direct electrical contact without requiring via holes. This integration eliminates the need for additional fabrication steps to create through-holes and fill them with conductive material, thereby reducing structural complexity and fabrication difficulty.
3Area of stationary object
If the transistor size is reduced to improve resolution, then display panel resolution improves, but parasitic capacitance effects become more significant and device performance degrades
Solution Approach 1:
The patent uses vertical stacking to separate gate and source/drain electrodes in the third dimension, eliminating parasitic capacitance between them. This allows horizontal dimensions to be reduced for miniaturization without the penalty of increased parasitic effects, as the harmful electromagnetic coupling has been eliminated through vertical separation.
Data Source
AI summary
The present disclosure provides a thin film transistor, a method of fabricating the same, an array substrate and a display device. The thin film transistor includes: source and drain electrodes in a same layer arranged on a base substrate; an active layer on the base substrate and in contact with the source and drain electrodes; a gate insulating layer at a side of the active layer away from the base substrate; a gate electrode at a side of the gate insulating layer away from the base substrate. Orthographic projections of the gate electrode, the source electrode and the drain electrode on the base substrate do not overlap with one another, and a region of the active layer not covered by the gate electrode, the source electrode and the drain electrode and at a side of the active layer away from the base substrate is subjected to conductorization.