Thin Film Transistor Non-Flat Contact Area
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Solution Overview
Problem
In thin film transistors used in flat panel displays, dry etching for contact hole formation leads to increased contact resistance and degraded electromigration resistance due to limited contact area between the channel and electrode lines, as there is no etching stopper film under the channel, unlike in CMOS processes.
Innovation Solution
The formation of connection sections with non-flat surfaces between the semiconductor layer and the source/drain electrodes, expanding the contact area and reducing contact resistance, while improving electromigration resistance by using dry etching to create through-holes with specific shapes such as comb-like or rounding surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dry etching is used to form contact holes, then layout efficiency is improved, but contact resistance increases and electromigration resistance is degraded
Solution Approach 1:
The patent applies curvature by forming rounded corners at the bottom of contact holes instead of sharp angles. This rounding of the contact hole geometry increases the contact area between the electrode line and semiconductor layer, thereby reducing contact resistance and improving electromigration resistance while maintaining the layout efficiency benefits of dry etching
Solution Approach 2:
The patent transitions from a simple planar contact interface to a three-dimensional rounded contact structure. By adding vertical curvature dimensions to the contact hole geometry, the effective contact area is increased without expanding the lateral footprint, thus improving electrical properties while maintaining layout efficiency
2Reliability
If wet etching is used to form contact holes, then contact resistance is reduced, but layout efficiency is degraded
Solution Approach 1:
The patent replaces the chemical etching mechanism of wet etching with a controlled physical etching process using dry etching. By combining dry etching with subsequent rounding treatments, the patent achieves the contact area benefits of wet etching while retaining the layout efficiency and precision control advantages of dry etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and enhances electromigration resistance by increasing the contact area between the semiconductor layer and electrodes, while maintaining improved layout efficiency achieved through dry etching.
Implementation Method 1
The contact hole is formed by, for example, wet etching (for example, Japanese Unexamined Patent Application Publication Nos. 2001-305576 and 2012-160679). In the case where the contact hole is formed by wet etching, however, layout efficiency has been low since it is necessary to consider a process margin for protection of a channel region from seepage of an etchant.
Data Source
AI summary
A thin film transistor includes: a gate electrode and a pair of source and drain electrodes; and a semiconductor layer having a channel formed therein, and having a pair of connection sections connected to the pair of source and drain electrodes, respectively, wherein one or both of opposed surfaces of the pair of connection sections is a non-flat surface.