TFT Backplane Notch Design for Via Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing TFT driving backplane manufacturing process requires strict alignment precision during photolithography and etching due to two-step holing, leading to potential short circuits and reduced product yield, especially in the 7T1C driver circuit where precise alignment of vias is critical.
Innovation Solution
A TFT driving backplane design that includes a notch on the top capacitor plate, allowing the sub-data line to be connected to the bottom capacitor plate via a first via extending from the notch, reducing the need for center alignment and minimizing the risk of short circuits, thereby relaxing alignment precision requirements and increasing the effective capacitive area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-step holing is performed at the center of the capacitor to connect the sub-data line and the bottom capacitor plate, then the connection is achieved, but the alignment precision requirement becomes extremely strict leading to short circuits and reduced product yield
Solution Approach 1:
The capacitor structure is segmented by introducing a notch that divides the top capacitor plate into two parts. This segmentation allows the first via to be positioned in the notch rather than at the center, eliminating the need for precise two-step alignment and reducing manufacturing complexity while maintaining electrical connection reliability
Solution Approach 2:
Instead of positioning the via at the center of the capacitor and requiring precise alignment through two-step holing, the invention inverts the approach by creating a notch in the top capacitor plate and positioning the via within the notch. This reverses the alignment challenge from a critical center-point alignment to a more tolerant notch-based alignment, significantly improving manufacturing yield
2Manufacturing precision
If the diameter of the first opening is made sufficiently large to facilitate manufacturing, then the alignment tolerance is improved, but the capacitive area is reduced
Solution Approach 1:
The top capacitor plate is segmented by introducing a notch, which separates the via opening from the capacitive area. This allows the first opening to be positioned in the notch region without encroaching on the capacitive plates, thereby maintaining both manufacturing tolerance and full capacitive area
Solution Approach 2:
The invention moves the via connection from the horizontal plane (center of capacitor) to a notched region that utilizes the vertical dimension and edge positioning. This dimensional shift allows the via to be positioned away from the capacitive area while maintaining electrical connection, effectively decoupling the via size from the capacitive area
Data Source
AI summary
Provided is a TFT driving backplane including, in top-to-bottom order, a sub-data line, a first insulating layer, a top capacitor plate, a second insulating layer and a bottom capacitor plate. In one side of the top capacitor plate is provided a notch filled upward by the first insulating layer provided with a first via extending vertically downward to the bottom capacitor plate. By moving the position where the sub-data line and the bottom capacitor plate are connected away from the top capacitor plate, holing is not required to be performed at the center of the capacitor and two-step opening alignment is avoided. Consequently, the requirement for alignment precision in photolithography is less critical, and the deviation due to two-step opening alignment is prevented. Meanwhile, by designing the margin and the one-way deviation, the short circuit in the capacitor can be avoided, and the effective capacitive area can be increased.