Thin Film Transistor Offset Region via Insulating Layer Thickness
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Solution Overview
Problem
Conventional methods for forming offset regions in thin film transistors require additional masks and complex processes, such as anodic oxidation, which complicate the manufacturing of polysilicon-based transistors used in OLED display devices, leading to performance degradation due to leakage currents and hot carriers.
Innovation Solution
A thin film transistor design where a first insulating layer is formed on the gate electrode with a predetermined thickness, allowing ion doping to create an offset region aligned with the gate electrode without the need for additional spacers or complex processes, and the thickness of this layer can be adjusted to control the offset region's width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods (spacer formation with additional mask and photo process or anodic oxidation) are used to form offset regions, then offset regions can be formed between channel and source/drain regions, but the manufacturing process becomes more complex
Solution Approach 1:
The patent removes the offset region formation process from the complex conventional methods (spacer formation with additional mask and photo process, or anodic oxidation) and extracts only the essential function: forming a doped region between the channel and source/drain regions. This is achieved by directly doping the semiconductor layer in the offset region area without requiring separate spacer formation steps, thereby simplifying the manufacturing process while maintaining the reliability benefit of preventing leakage currents and hot carriers.
Solution Approach 2:
The patent merges the offset region formation with the main doping process. Instead of forming spacers first and then doping, or performing separate anodic oxidation steps, the invention combines these functions into a single integrated doping step where ions are implanted directly into the semiconductor layer to form both the source/drain regions and the offset regions in one process sequence, reducing manufacturing complexity.
2Manufacturing precision
If additional masks and photo processes are used to form spacers for offset regions, then offset regions can be formed, but the number of manufacturing steps increases
Solution Approach 1:
The patent extracts the offset region formation from the multi-step spacer formation process (which includes additional masks and photo processes). By directly doping the semiconductor layer in the offset region area without requiring separate spacer formation steps, the invention maintains precise alignment with the gate electrode while reducing the number of manufacturing steps and improving productivity.
Solution Approach 2:
The patent performs preliminary positioning of the doping area using the gate electrode structure itself as a reference. The offset region is formed by doping areas adjacent to the gate electrode before source/drain electrode formation, using the gate electrode's position to define the offset region boundaries, thereby achieving precise alignment without additional masking steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces the complexity of forming offset regions, and helps in adjusting their width, thereby improving the performance of thin film transistors and OLED display devices by minimizing leakage currents and hot carriers.
Implementation Method 1
ion doping may be performed on predetermined regions of the polysilicon layer to form source/drain regions
Data Source
AI summary
A thin film transistor, a method of fabricating the same, and an organic light emitting diode (OLED) display device including the same. The thin film transistor includes a substrate; a semiconductor layer disposed on the substrate and including a channel region; source/drain regions including ions and an offset region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; a first insulating layer disposed on the gate electrode; a second insulating layer disposed on the first insulating layer; and source/drain electrodes disposed on the second insulating layer, and electrically connected to the source/drain regions of the semiconductor layer, respectively. The sum of thicknesses of the gate insulating layer and the first insulating layer that are on the source/drain regions is less than the vertical dispersion depth of the ions included in the source/drain regions.