Thin-Film Transistor Ohmic Contact Layer Design
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Solution Overview
Problem
Conventional thin-film transistors in liquid crystal display devices have high contact impedance between the channel layer and electrodes, leading to increased drive voltage and power consumption.
Innovation Solution
The design includes a first and second ohmic contact layer between the source and drain electrodes and the channel layer, respectively, along with a passivation layer, to reduce contact resistance, and uses a metal oxide channel layer with ultraviolet light treatment to form these layers, optimizing the transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the channel layer is directly contacted with source and drain electrodes, then the device structure is simple, but the contact impedance is high leading to increased power consumption
Solution Approach 1:
An ohmic contact layer is introduced as an intermediary between the channel layer and the source/drain electrodes. This intermediate layer has high carrier concentration and excellent ohmic contact properties, which reduces contact impedance and power consumption while maintaining structural simplicity.
Solution Approach 2:
The electrical parameters of the contact interface are changed by introducing the ohmic contact layer with specifically tailored properties (high carrier concentration, appropriate thickness). This transforms the high-impedance Schottky contact into a low-impedance ohmic contact, reducing power consumption without significantly increasing device complexity.
2Ease of manufacture
If the channel layer is directly contacted with source and drain electrodes, then the manufacturing process is simple, but the contact resistance is high requiring larger drive voltage
Solution Approach 1:
The ohmic contact layer serves as a mediator that facilitates better electrical contact between the electrodes and channel layer. It enables lower drive voltage requirements while adding minimal complexity to the manufacturing process, as it can be formed using standard sputtering techniques followed by UV treatment.
Solution Approach 2:
UV light treatment is applied to the ohmic contact layer before final electrode formation to pre-modify its electrical properties. This preliminary action enhances carrier concentration and improves contact characteristics, allowing for lower drive voltage in subsequent operation without requiring complex post-processing steps.
3Device complexity
If conventional contact structure is used, then the device structure is simple, but parasitic capacitance is high affecting display performance
Solution Approach 1:
The ohmic contact layer acts as an intermediary that reduces parasitic capacitance at the electrode-channel interface. By providing a dedicated contact pathway with optimized electrical properties, it minimizes unwanted capacitive effects that would otherwise degrade display performance, while keeping the overall structure relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption by minimizing contact resistance and parasitic capacitance, enabling more efficient operation of the liquid crystal display panel.
Implementation Method 1
The first ohmic contact layer is arranged between the source electrode and the channel layer... The first ohmic contact layer functions to reduce contact resistance between the source electrode and the channel layer
Implementation Method 2
The second ohmic contact layer is arranged between the drain electrode and the channel layer... The second ohmic contact layer functions to reduce contact resistance between the drain electrode and the channel layer
Implementation Method 3
The passivation layer covers the channel layer, the source electrode, the drain electrode, the first ohmic contact layer, and the second ohmic contact layer
Data Source
AI summary
A thin-film transistor, a liquid crystal display panel, and a thin-film transistor manufacturing method are provided. The thin-film transistor includes a base plate and a gate electrode, a gate insulation layer, a source electrode, a drain electrode, a channel layer, first and second ohmic contact layers, a passivation layer, and a pixel electrode that are arranged on the same side of the base plate. The gate insulation layer covers the gate electrode that is on the base plate. The source electrode, the drain electrode, the channel layer, the first and second ohmic contact layers are arranged on the gate insulation layer. The channel layer is arranged between the source electrode and the drain electrode and corresponds to the gate electrode. The first ohmic contact layer is arranged between the source electrode and the channel layer. The second ohmic contact layer is arranged between the drain electrode and the channel layer.