TFT Array Substrate Pad Trench Layout for Reliable Bonding
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Solution Overview
Problem
In display panels, the thicker planarization layer can cover the edges of pads, leading to insufficient bonding pressure between electrodes and pads, resulting in poor electrical contact or contact failure due to the height difference between the planarization layer and the pads.
Innovation Solution
The TFT array substrate incorporates trenches in the insulating layer to prevent the planarization layer from covering the pads, ensuring that the bonding pressure is concentrated on the pads, and the display panel uses an anisotropic conductive film for electrical connection, with trenches on the insulating layer reducing the height difference between the planarization layer and the pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker planarization layer is used to cover the metal electrode, then the electrode is protected from etchant exposure, but the planarization layer covers the pad edges causing insufficient bonding pressure concentration
Solution Approach 1:
The planarization layer is segmented by introducing trenches that divide it into separate regions. These trenches create distinct zones where the planarization layer can cover the electrode while leaving the pad areas exposed, thus maintaining both electrode protection and bonding pressure concentration.
Solution Approach 2:
The planarization layer is applied selectively to different areas with different properties. Over the electrode, it provides thick coverage for protection, while over the pad areas, it is removed or reduced to maintain proper bonding characteristics. This local differentiation resolves the contradiction between protection and bonding precision.
2Shape
If the planarization layer covers the pad edges, then surface flatness is improved, but bonding pressure spreads to non-pad areas causing poor contact
Solution Approach 1:
The planarization layer is divided into covered regions (over electrode) and exposed regions (over pad) through trenches. This segmentation allows the surface to be flat where needed while maintaining proper bonding pressure distribution at the pad interfaces.
Solution Approach 2:
The planarization layer is selectively removed or not formed over the pad edges by defining trenches. This extraction of the planarization layer from specific areas allows bonding pressure to concentrate on the pads without spreading to surrounding regions, ensuring reliable electrical contact.
3Reliability
If bonding pressure is insufficient due to planarization layer coverage, then contact between electrode and pad fails, but increasing pressure may damage other components
Solution Approach 1:
The planarization layer is removed or reduced over the pad areas through defined trenches, creating localized zones where bonding pressure can be effectively applied without being distributed to surrounding components. This ensures sufficient contact pressure for reliable electrical connection while preventing damage to other parts of the structure.
Data Source
AI summary
The present disclosure relates to a TFT array substrate and a display panel including the same. The TFT array substrate includes a first substrate and a circuit layer disposed on a side of the first substrate; wherein the circuit layer comprises a first electrode layer, an insulating layer, a first pad layer, and a planarization layer; the first electrode layer comprises a plurality of first electrodes disposed on the side of the first substrate, and the first electrodes are electrodes of thin film transistors in the TFT array substrate; the insulating layer is disposed on a side of the first electrode layer away from the first substrate; the first pad layer comprises a plurality of first pads disposed on a side of the insulating layer away from the first electrode layer; the plurality of first pads are electrically connected to the plurality of first electrodes through contact holes respectively penetrating the insulating layer; the planarization layer is disposed on the side of the insulating layer away from the first electrode layer; the insulating layer is provided with a plurality of trenches, and a projection of each of the trenches on the first substrate respectively covers a projection of a corresponding edge of the first pads on the first substrate.