TFT Array Panel Electrode Patterning with Fewer Photo-Etch Steps
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Solution Overview
Problem
The manufacturing of transflective LCDs requires seven photo-etching processes, making it more costly and time-consuming compared to transmissive LCDs, which typically use four or five photo-etching processes.
Innovation Solution
A method for manufacturing a TFT array panel that reduces the number of photo-etching steps by forming multiple thin film transistors with gate, source, and drain electrodes, followed by selective etching using a photoresist layer as an etch blocker, and using specific etchants and conductive materials like ITO and Al to efficiently pattern the conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If seven photo-etching processes are used for manufacturing transflective LCDs, then the quality and functionality of the display are improved, but the manufacturing cost and time increase
Solution Approach 1:
The patent combines the formation of transmission electrode and reflection electrode into a single photo-etching process. By depositing both ITO and Al layers sequentially and using a single photoresist pattern, both electrodes are patterned simultaneously, reducing the process count from seven to four photo-etching steps while maintaining electrode quality and display functionality
Solution Approach 2:
The patent performs preliminary deposition of multiple conductive layers (ITO and Al) before the photo-etching process. This preliminary action allows both transmission and reflection electrodes to be formed in advance, enabling their simultaneous patterning in one photo-etching step and eliminating the need for separate etching processes
2Adaptability or versatility
If seven photo-etching processes are used for manufacturing transflective LCDs, then the display functionality is improved, but the manufacturing cost increases
Solution Approach 1:
The patent merges the patterning of transmission and reflection electrodes into one photo-etching process by using sequential layer deposition and a single photoresist mask, reducing the number of expensive photo-etching steps from seven to four and thereby lowering manufacturing costs while preserving full display functionality
Solution Approach 2:
The patent creates a multi-functional photoresist pattern that serves as a single mask for patterning both ITO and Al layers. This universal approach allows one photoresist layer to perform the function of multiple separate masks, reducing process complexity and manufacturing cost
3Manufacturing precision
If conventional photo-etching processes are used, then electrode patterning is achieved, but undesirable lifting of reflection electrodes occurs
Solution Approach 1:
The patent performs preliminary deposition of the Al reflection electrode layer on top of the ITO transmission electrode layer before photo-etching. This preliminary stacking ensures that the reflection electrode is already in place and properly positioned, preventing lifting during the etching process since both layers are patterned simultaneously in one step rather than separately
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method decreases the number of photo-etching steps, reducing manufacturing costs and time while maintaining the quality of the TFT array panel, and prevents undesirable lifting of reflection electrodes.
Implementation Method 1
forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers
Implementation Method 2
selectively etching the second conductive layer with a first etchant; selectively etching the first conductive layer with a second etchant
Implementation Method 3
sequentially depositing an amorphous ITO layer and a first conductive layer on the organic insulating layer
Data Source
AI summary
The present invention provides a method of manufacturing a TFT array panel in a cost-effective manner. The method includes: forming thin film transistors each having a gate electrode, a source electrode, and a drain electrode; forming an insulating layer on the thin film transistors; forming a first conductive layer electrically connected to the drain electrodes on the insulating layer; forming a second conductive layer on the first conductive layer; forming a photoresist layer including first portions and second portions thinner than the first portions; selectively etching the second conductive layer with a first etchant by using the photoresist layer as an etch blocker; and selectively etching the first conductive layer with a second etchant by using the photoresist layer and the second conductive layer as etch blockers.