TFT Panel Interlayer Insulation with Variable Dielectric Constants
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Solution Overview
Problem
Active matrix OLEDs face challenges in reducing parasitic capacitance in TFT panels while maintaining high capacitor capacitance, which degrades the quality of the display due to the use of high dielectric materials in interlayer insulation layers.
Innovation Solution
The implementation of interlayer insulation layers with different dielectric constants in TFT and capacitor regions of the TFT panel, where the capacitor region uses a high dielectric material to increase capacitance and the TFT region uses a lower dielectric material to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high dielectric material is used for the interlayer insulation layer to increase capacitor capacitance, then the capacitance of the capacitor is improved, but the parasitic capacitance in the TFT increases, degrading the TFT panel characteristics
Solution Approach 1:
The patent applies local quality by using different dielectric materials with different dielectric constants in different regions of the interlayer insulation layer. Specifically, a first dielectric material with a higher dielectric constant is used in the capacitor region to increase capacitance, while a second dielectric material with a lower dielectric constant is used in the TFT region to minimize parasitic capacitance. This regional differentiation resolves the contradiction by optimizing each region's electrical properties according to its specific functional requirements.
Solution Approach 2:
The interlayer insulation layer is segmented into multiple regions with different dielectric materials. The patent divides the interlayer insulation layer into a capacitor region portion and a TFT region portion, each filled with appropriately selected dielectric materials. This segmentation allows independent optimization of capacitance in the capacitor region and parasitic capacitance reduction in the TFT region, effectively resolving the technical contradiction.
2Quantity of substance
If a high dielectric material is used uniformly across the TFT panel to increase capacitor capacitance, then the capacitance is improved, but the TFT characteristics are degraded due to increased parasitic capacitance
Solution Approach 1:
The patent implements local quality by selecting different dielectric materials for different functional regions. The capacitor region uses a first dielectric material (e.g., silicon nitride or silicon oxynitride) with higher dielectric constant to maximize capacitance, while the TFT region uses a second dielectric material (e.g., silicon oxide) with lower dielectric constant to maintain low parasitic capacitance and preserve TFT characteristics. This localized material selection simultaneously achieves high capacitor capacitance and reliable TFT performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the capacitance of the capacitor while reducing parasitic capacitance in the TFT, thereby enhancing the overall quality and performance of the active matrix OLED.
Implementation Method 1
a capacitor interlayer insulation layer formed on the capacitor lower electrode, wherein the capacitor interlayer insulation layer has a different dielectric constant from the TFT interlayer insulation layer
Data Source
AI summary
Provided are a thin film transistor (TFT) panel, a method of fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT panel has a TFT region and a capacitor region. A TFT is formed in the TFT region and a capacitor is formed in the capacitor region. The TFT includes an active layer that includes a source and a drain regions. A gate insulation layer is formed on the active layer, and a gate electrode is formed on the gate insulation layer over the active layer. A source and a drain electrodes are formed over the active layer, and connected to the source and drain regions, respectively. In the TFT region, an interlayer insulation layer is formed between the gate electrode and the source/drain electrodes. In the capacitor region, an interlayer insulation layer is formed between a capacitor lower electrode and a capacitor upper electrode to form a capacitor. The interlayer insulation layers of the TFT region and the capacitor region have different layer structures and have different dielectric constants. Therefore, the capacitor region can have higher capacitance while the TFT region can have lower capacitance to reduce parasitic capacitance.