TFT Panel Sidewall Coverage Prevents Active Layer Protrusion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing processes for thin film transistor panels, which rely on multiple photolithography steps, result in increased processing time and cost, and can cause the active layer to protrude beyond the source and drain electrodes, leading to image degradation.
Innovation Solution
A thin film transistor panel design where the source and drain electrodes directly contact the entire surface area of the semiconductor layer's sidewalls, reducing the need for additional patterning steps and preventing the semiconductor layer from protruding, achieved through a method involving multiple protective films and careful etching to form contact holes and expose the drain electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography processes are used to fabricate TFT, then the TFT structure can be precisely formed, but the processing time and manufacturing cost increase
Solution Approach 1:
The patent combines the semiconductor layer and metal layer into a single simultaneous patterning process. The multi-layer conductive structure is formed in one photolithography step rather than separate steps, merging multiple fabrication operations into a unified process that reduces time while maintaining precision through the integrated design
Solution Approach 2:
The multi-layer conductive structure serves multiple functions: it acts as both the semiconductor layer and metal layer simultaneously, providing both electrical conduction and structural definition. This multi-functional approach eliminates the need for separate patterning steps for each layer, reducing processing time while maintaining manufacturing precision
2Productivity
If semiconductor layer and metal layer are simultaneously patterned, then the number of photolithography processes is reduced, but the active layer protrudes beyond the source and drain electrodes causing image degradation
Solution Approach 1:
The patent introduces a vertical multi-layer dimension to solve the horizontal alignment problem. By stacking conductive layers at different heights with varying widths, the structure achieves precise lateral boundaries through vertical layering rather than relying solely on horizontal photolithography alignment, thus preventing protrusion while maintaining manufacturing efficiency
Solution Approach 2:
Different portions of the conductive structure have different widths at different vertical levels. The upper layers have narrower widths that precisely define the source and drain electrode boundaries, while lower layers provide broader support. This local variation in dimensions ensures precise electrode alignment without requiring multiple photolithography steps
3Ease of manufacture
If the semiconductor layer protrudes beyond the source and drain electrodes, then the manufacturing process is simpler, but image degradation occurs
Solution Approach 1:
The patent uses vertical layering to control the horizontal extent of the active layer. By positioning the semiconductor layer between narrower metal layers in the vertical dimension, the structure automatically confines the active layer within the electrode boundaries without complex lateral patterning, maintaining manufacturing simplicity while ensuring image quality
Solution Approach 2:
The multi-layer conductive structure acts as an intermediary that mediates between the semiconductor layer and the external environment. The stacked conductive layers provide precise boundary definition and electrical isolation, preventing the semiconductor layer from protruding while maintaining the simplicity of the patterning process and ensuring reliable image display
Data Source
AI summary
A thin film transistor panel includes; an insulating substrate, a gate line including a gate electrode disposed on the insulating substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including a sidewall, a data line including a source electrode disposed on the semiconductor layer, a drain electrode disposed substantially opposite to and spaced apart from the source electrode, a first protective film disposed on the data line, the first protective film including a sidewall, a second protective film disposed on the first protective film and including a sidewall, and a pixel electrode electrically connected to the drain electrode, wherein the sidewall of the second protective film is disposed inside an area where the sidewall of the first protective film is disposed, and the source electrode and the drain electrode cover the sidewall of the semiconductor layer.