Thin Film Transistor Parasitic Capacitance Reduction
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Solution Overview
Problem
Thin film transistors experience decreased performance due to high parasitic capacitance between the source and gate electrodes and between the drain and gate electrodes, which interferes with carrier movement.
Innovation Solution
The thin film transistor design includes the source and drain electrodes disposed in the same layer as the gate electrode, with a passivation layer of low dielectric constant (less than 2.8) to reduce parasitic capacitance, and a gate insulating layer of high dielectric constant (greater than 3.9) to block current and reduce leakage, along with connection patterns that connect the active layer to the electrodes through via holes, effectively minimizing the influence of parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thin film transistor structure is used with standard dielectric materials, then current blocking and leakage reduction are achieved, but parasitic capacitance between source/drain and gate electrodes becomes high, degrading transistor performance
Solution Approach 1:
The patent applies different dielectric materials with different properties to different regions: a high dielectric constant material (≥3.9, e.g., Al2O3, Ta2O5, HfO2) for the gate insulating layer to block current and reduce leakage, and a low dielectric constant material (<2.8, e.g., SiOC) for the passivation layer to reduce parasitic capacitance. This local differentiation of material properties resolves the contradiction between current blocking and parasitic capacitance reduction.
Solution Approach 2:
The patent uses composite dielectric structures combining high-k gate insulating layer with low-k passivation layer. This composite approach allows simultaneous achievement of effective current blocking (via high-k material) and parasitic capacitance reduction (via low-k material), directly resolving the technical contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces parasitic capacitance, enhances the performance of the thin film transistor, and protects the active layer from environmental influences by completely covering it with the passivation layer.
Implementation Method 1
Thin film transistors experience decreased performance due to high parasitic capacitance between the source and gate electrodes and between the drain and gate electrodes
Implementation Method 2
a gate insulating layer of high dielectric constant (greater than 3.9) to block current and reduce leakage
Data Source
AI summary
A thin film transistor and a fabrication method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a gate electrode (2), a source electrode (5) and a drain electrode (6) disposed in a same layer on a base substrate (1); a gate insulating layer (3) disposed on the gate electrode (2), the source electrode (5) and the drain electrode (6); an active layer (4) disposed on the gate insulating layer (3); a passivation layer (7) disposed on the active layer (4) and the gate insulating layer (3). A first via hole (81) and a second via hole (91) are disposed in the passivation layer (7); a third via hole (82) and a fourth via hole (92) are disposed in the passivation layer (7) and the gate insulating layer (3); a first connection pattern (8) and a second connection pattern (9) are disposed on the passivation layer (7); the first connection pattern (8) is connected with the active layer (4) and the source electrode (5) through the first via hole (81) and the third via hole (82) respectively; the second connection pattern (9) is connected with the active layer (4) and the drain electrode (6) through the second via hole (91) and the fourth via hole (92) respectively. The thin film transistor effectively reduces the influence of the parasitic capacitance between the source electrode and the gate electrode and the parasitic capacitance between the drain electrode and the gate electrode on the thin film transistor.