TFT Substrate Passivation Structure for Contact Area and Etch Control

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Solution Overview

Problem

The existing methods for fabricating thin film transistor (TFT) array substrates face challenges in increasing the driving margin and ensuring a sufficiently large contact area between conductive materials, which can lead to over-etching of the gate insulating layer and damage to data interconnection lines, resulting in reduced manufacturing efficiency and increased costs.

Innovation Solution

A TFT substrate design that includes a gate interconnection line, a semiconductor layer, and passivation layers with a porous lattice structure, where the outer sidewalls of the second passivation layer are positioned inside the outer sidewalls of the first passivation layer, allowing for controlled etching and preventing over-etching, while maintaining a large contact area for easy lift-off and reducing damage to data interconnection lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the passivation film is over-etched to form a sufficiently large undercut under the photoresist pattern, then the contact area between the photoresist stripper and the photoresist pattern is increased, but the gate insulating layer is over-etched and its thickness becomes non-uniform, reducing the driving margin

Engineering Contradiction:
Improvecontact area between photoresist stripper and photoresist patternVSAvoidthickness uniformity of gate insulating layer
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The passivation film is divided into two separate layers: a first passivation layer (dense structure) and a second passivation layer (porous lattice structure). The second layer is specifically designed to be over-etched during the lift-off process, creating the necessary undercut for photoresist stripper contact, while the first layer remains protected and maintains its original thickness to preserve the driving margin.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the passivation structure are given different etching characteristics. The second passivation layer has a porous lattice structure that makes it more susceptible to over-etching, while the first passivation layer has a dense structure that resists over-etching. This local differentiation allows selective removal where needed while protecting critical areas.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the passivation film is over-etched to form an undercut, then the contact area is increased for better lift-off, but the data interconnection line is damaged by over-etching, causing contact failure

Engineering Contradiction:
Improvecontact areaVSAvoidcontact reliability of data interconnection line
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The passivation structure is segmented into two layers with different protective functions. The first passivation layer acts as a protective barrier over the data interconnection line, preventing damage during over-etching of the second layer, while still allowing the second layer to provide the necessary undercut for lift-off contact.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first passivation layer is deposited beforehand to provide a protective cushion over the data interconnection line. This protective layer prevents direct damage to the data line during the over-etching process, ensuring contact reliability while still allowing the second layer to be over-etched for adequate lift-off contact area.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If a single passivation layer is used, then the manufacturing process is simpler, but it cannot simultaneously provide sufficient undercut for lift-off and protect the gate insulating layer from over-etching

Engineering Contradiction:
Improveprocess simplicityVSAvoiddual function of undercut formation and protection
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The single passivation layer is segmented into two functional layers: the first passivation layer provides protection against over-etching, while the second passivation layer provides the porous structure that enables controlled over-etching for undercut formation. This segmentation allows both functions to coexist.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The two-layer passivation structure achieves multi-functionality: the first layer serves as a protective barrier, the second layer serves as an etchable undercut-forming layer, and together they provide both protection and adequate contact area for lift-off, making the structure adaptable to multiple requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the driving margin, prevents over-etching of the gate insulating layer, and ensures a reliable contact area between conductive materials, thereby improving manufacturing efficiency and reducing costs by preventing damage to data interconnection lines.

Implementation Method 1

the second passivation film has more porous lattice structure than that of the first passivation layer

Methodology Applied
Scientific EffectPorous lattice structure: Porosity

Data Source

PatentUS8450129B2Thin film transistor substrate and manufacturing method thereof
Publication Date: 2013.05.28 SAMSUNG DISPLAY CO LTD
  • US8450129B2 patent drawing
  • US8450129B2 patent drawing
  • US8450129B2 patent drawing

AI summary

A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.