TFT Pixel Structure Hollow Gate Overlap
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Solution Overview
Problem
Existing array substrates in TFT-LCDs exhibit high coupling capacitance between the gate and source/drain layers due to overlapping regions, leading to insufficient TFT driving capability and slow charging speed, causing deviations in pixel voltage and gray scale representation.
Innovation Solution
A pixel structure is introduced with a hollow structure in the overlapping region between the gate and source/drain layers, reducing coupling capacitance and enhancing TFT driving and charging capabilities by arranging openings of various shapes on the gate or source/drain layers, and optimizing the channel length and source width to minimize leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an overlapping region is present between the gate layer and the source/drain layer, then the TFT structure is complete and functional, but the coupling capacitance becomes large resulting in insufficient TFT driving capability and slow charging speed
Solution Approach 1:
The patent extracts the harmful overlapping region between the gate layer and source/drain layer by introducing a hollow structure that removes material from this region. This extraction reduces the coupling capacitance formed by the overlapping conductive layers while preserving the essential TFT functionality through the remaining structural elements.
Solution Approach 2:
The patent introduces a hollow structure within the overlapping region that creates a porous or cavity-containing configuration. This porous approach reduces the effective overlapping area between conductive layers, thereby decreasing coupling capacitance while maintaining the structural integrity and electrical functionality of the TFT.
2Productivity
If the overlapping area between source/drain layer and gate layer is reduced, then coupling capacitance decreases and TFT driving capability improves, but the area of the gate and source/drain structures must be optimized to avoid increasing leakage current
Solution Approach 1:
The patent applies local quality by introducing the hollow structure specifically in the overlapping region where coupling capacitance is generated, while maintaining the necessary conductive pathways and dimensional specifications in other critical areas. This localized modification reduces capacitance without compromising the structural integrity needed to prevent leakage current.
Solution Approach 2:
The patent modifies geometric parameters by introducing a hollow structure with specific dimensions and positioning within the overlapping region. By carefully controlling the size, shape, and location of this hollow structure, the patent optimizes the balance between reducing coupling capacitance (improving charging speed) and maintaining sufficient overlap to prevent leakage current.
Data Source
AI summary
A pixel structure, an array substrate and a display device is provided. The pixel structure includes a base substrate, and a gate layer and a source/drain layer arranged on the base substrate. An overlapping region is present between the gate layer and the source/drain layer, and the gate layer and/or the source/drain layer comprises a hollow structure located in the overlapping region.