TFT Pixel Structure with Three Photomasks and Integrated Storage Capacitor

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Solution Overview

Problem

The high cost of photomasks in TFT-LCD manufacturing, particularly due to the large number required, poses a significant challenge for manufacturers aiming to reduce process steps and fabrication costs as they scale up production.

Innovation Solution

A pixel structure is designed using a simplified configuration that employs only three photomasks, incorporating a light-shielding layer, channel layer, source and drain, gate dielectric layer, and patterned transparent conductive layer, with the gate and scan lines cut out partially to avoid electrical contact and reduce leakage current, allowing for simultaneous formation of the pixel structure and storage capacitor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional TFT fabrication processes are used, then the pixel structure can be formed, but the number of photomasks required is high (4-7 photomasks), leading to high fabrication costs

Engineering Contradiction:
Improvefabrication costVSAvoidnumber of photomasks
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The invention merges the formation of the pixel structure and storage capacitor into a single integrated structure. The gate electrode serves dual purposes: as the gate of the TFT and as one electrode of the storage capacitor. This integration eliminates the need for separate capacitor electrodes and reduces the number of photomasks from 4-7 to just 3 photomasks, directly addressing the contradiction between fabrication complexity and manufacturing ease

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate electrode is designed to perform multiple functions simultaneously: it acts as the control gate for the TFT switching operation and as one of the electrodes for the storage capacitor. This multi-functionality reduces the total number of components and photomasks required, resolving the technical contradiction by reducing device complexity while maintaining manufacturing feasibility

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the gate and scan lines are fully connected, then the pixel structure can be formed, but leakage current occurs and the pixel structure may be disabled

Engineering Contradiction:
Improvepixel structure functionalityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The invention extracts or removes portions of the gate electrode and scan line that would otherwise create unwanted electrical contacts. By cutting out these specific portions, the design eliminates direct electrical contact between the gate electrode and scan line, preventing leakage current while maintaining the necessary electrical connections for TFT operation and storage capacitor function

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The gate electrode and scan line are segmented into separate portions with intentional gaps. The gate electrode is divided into a first portion and second portion, and the scan line is divided into a third portion and fourth portion, with specific portions cut out to prevent unwanted electrical contact. This segmentation approach maintains necessary electrical connections while eliminating leakage paths, resolving the contradiction between reliability and harmful factors

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8586986B2Pixel structure
Publication Date: 2013.11.19 AU OPTRONICS CORP
  • US8586986B2 patent drawing
  • US8586986B2 patent drawing
  • US8586986B2 patent drawing

AI summary

A pixel structure having the following structure is provided. A light-shielding layer with a flat layer covering thereon is disposed on a substrate. A channel layer, a data line and a first pad are disposed on the flat layer. A source and a drain partially cover two sides of the channel layer. A gate dielectric layer with a gate, a scan line and a second pad disposed thereon covering the channel layer, the source and the data line exposes the drain and the first pad. A protection layer covering the gate and the scan line exposes the drain, the first and second pads. A patterned transparent conductive layer includes a pixel electrode disposed on the protection layer, a first retain portion disposed on the first pad and a second retain portion disposed on the second pad.