TFT Array Panel Projection for Lateral Visibility
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Solution Overview
Problem
Vertical alignment liquid crystal display (VA LCD) has relatively poor lateral visibility compared to front visibility, and existing solutions for improving this, such as dividing a pixel into two subpixels with different voltages, face complications in voltage control and uniformity.
Innovation Solution
A thin film transistor array panel design featuring a substrate with specific gate and data lines, thin film transistors, and pixel electrodes, including a projection on the drain electrode that ensures uniform overlapping areas regardless of misalignment, allowing for differential voltage control between subpixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If a pixel is divided into two subpixels with different voltages to improve lateral visibility, then lateral visibility is improved, but voltage control complexity increases
Solution Approach 1:
The pixel is divided into two subpixels (first subpixel electrode and second subpixel electrode) with different voltage control capabilities. The second subpixel electrode includes a projection that overlaps with the drain electrode to form a capacitor, enabling independent voltage control for lateral visibility improvement
Solution Approach 2:
The invention changes the voltage parameter by applying different voltages to the first and second subpixel electrodes. The second subpixel electrode can be supplied with a different voltage through the capacitor formed by the projection and drain electrode, enabling voltage differentiation to improve lateral visibility
2Ease of operation
If capacitors are used to differentiate voltages between subpixels, then voltage differentiation is achieved, but voltage uniformity deteriorates
Solution Approach 1:
The projection on the second subpixel electrode creates a localized capacitor structure that overlaps with the drain electrode. This local capacitor provides voltage differentiation only where needed (in the overlapping region) while maintaining uniform voltage distribution across the entire pixel through proper geometric design
Solution Approach 2:
The second subpixel electrode includes an asymmetric projection structure that overlaps with the drain electrode, creating an asymmetric capacitor configuration. This asymmetric design enables voltage differentiation between subpixels while the symmetric arrangement of edge portions ensures uniform overlapping areas and maintains voltage uniformity
3Manufacturing precision
If misalignment between projection and drain electrode occurs, then manufacturing precision deteriorates, but overlapping area uniformity can be maintained through geometric design
Solution Approach 1:
The projection is designed with edge portions that are substantially parallel to the edges of the drain electrode, creating a geometric configuration that compensates for potential misalignment. This design provides a cushioning effect that maintains uniform overlapping areas even when alignment precision is not perfect during manufacturing
Solution Approach 2:
The projection includes a first pair of edge portions that are substantially parallel to each other and meet the first edge of the drain electrode, and a second pair of edge portions that are substantially parallel to each other and meet the second edge of the drain electrode. This symmetric-asymmetric geometric design ensures that the overlapping area remains uniform regardless of misalignment, as the parallel edge portions compensate for positional deviations
Data Source
AI summary
A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.