Thin Film Transistor Recessed Cushion Layer Gap Control
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Solution Overview
Problem
The existing methods for manufacturing thin film transistors result in large gaps between the source and drain due to low precision in patterning treatment, leading to larger transistor sizes.
Innovation Solution
A thin film transistor design with a recessed base cushion layer and a deposition method for forming the source-drain layer, allowing precise control of the gap between the source and drain, reducing the transistor size by using a base insulating layer with partition walls that overlap the recessed portion, enabling accurate deposition of the source-drain layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional patterning treatment is used to form the source-drain layer, then the manufacturing process is simple, but the gap between source and drain becomes large due to low precision
Solution Approach 1:
The base cushion layer is pre-formed with a recessed portion at the desired gap location before depositing the source-drain layer. This preliminary structural preparation enables precise gap control during subsequent deposition without requiring high-precision patterning, thus resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The base insulating layer with partition walls acts as an intermediary structure that bridges the recessed portion of the base cushion layer and the source-drain layer. The partition walls provide physical guidance for material deposition, enabling precise gap formation while simplifying the overall manufacturing process
2Length of moving object
If the gap between source and drain is reduced to micron or nano-scale, then the transistor size decreases, but the manufacturing precision requirement increases
Solution Approach 1:
The recessed portion is pre-formed in the base cushion layer at the exact location where the narrow gap should be. This preliminary action defines the gap position and dimensions before source-drain material deposition, enabling micron or nano-scale gap formation without requiring extremely high deposition precision
Solution Approach 2:
The patent replaces traditional mechanical patterning methods with a deposition-based approach guided by the pre-formed recessed structure. This substitution allows for more precise control of small dimensions through controlled material deposition rather than mechanical removal, reducing the transistor size while maintaining manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller thin film transistor size with a narrow channel width, improving precision and reducing the gap between the source and drain to micron or nano-scale dimensions, while simplifying the manufacturing process compared to traditional patterning methods.
Implementation Method 1
a deposition method for forming the source-drain layer, allowing precise control of the gap between the source and drain
Data Source
AI summary
Provided are a thin film transistor including: a base cushion layer having a recessed portion, base insulating layer, source-drain layer and active layer. The base insulating layer is located on a side of the base cushion layer where the recessed portion is located, and has a first and second partition walls that are spaced apart, and an orthographic projection region of a gap region between the first and second partition walls onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first and second partition walls onto the base cushion layer partially overlap with the recessed portion region; and both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer.