Thin Film Transistor Reducing Pattern for Stability
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Solution Overview
Problem
Existing thin film transistors, particularly oxide semiconductor thin film transistors, face challenges in reliability due to deviations in the conductorization area, leading to instability and mobility issues, which affect the performance and uniformity of display devices.
Innovation Solution
A thin film transistor design that incorporates a reducing pattern to selectively conductorize the active layer, controlling the size and position of the conductorization portion and forming diffusion portions between the channel and conductorization portions to prevent edge conductorization, thereby enhancing reliability and channel length control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a top gate type oxide semiconductor thin film transistor is fabricated in a coplanar structure, then the device can be manufactured with relatively low cost and low temperature process, but the conductorization area may deviate leading to degraded stability and mobility
Solution Approach 1:
The patent applies local quality by creating distinct regions within the active layer with different conductivity characteristics. The channel region is maintained as non-conductorized oxide semiconductor while the source and drain regions are selectively conductorized through controlled oxygen deficiency, achieving both manufacturability and device reliability through localized property differentiation.
Solution Approach 2:
The patent utilizes parameter changes by controlling the oxygen content and conductivity type in different regions of the oxide semiconductor active layer. By adjusting the oxygen deficiency level through selective doping or plasma treatment, the patent transforms the electrical parameters (conductivity, carrier concentration) to achieve stable threshold voltage and high mobility simultaneously.
2Device complexity
If the conductorization area is not precisely controlled, then the fabrication process is simpler, but the threshold voltage changes and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-defining the conductorization regions through masking patterns or selective doping before the main transistor fabrication steps. This preliminary region definition ensures precise control over where conductorization occurs, preventing threshold voltage shifts while maintaining a manageable fabrication process.
Solution Approach 2:
The patent introduces an intermediary layer or intermediate processing step (such as a selective masking layer or plasma treatment layer) that mediates between the simple coplanar fabrication approach and the precise conductorization area control requirement. This intermediary enables accurate region definition without significantly complicating the overall process.
3Productivity
If amorphous silicon is used as active layer, then the fabricating process time is short and production cost is low, but the current driving capacity is insufficient due to low mobility
Solution Approach 1:
The patent changes the material parameter from amorphous silicon to oxide semiconductor (such as IGZO), which inherently provides higher carrier mobility while maintaining compatibility with low-temperature fabrication processes. This material substitution resolves the contradiction by achieving both high productivity and high current driving capacity.
Solution Approach 2:
The patent employs composite material structures by combining oxide semiconductor layers with selective doping regions or multi-layer configurations. This composite approach maintains the ease of fabrication associated with oxide semiconductors while enhancing the current driving capacity through optimized material composition and structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves the reliability and performance of thin film transistors by elaborately controlling the channel length and preventing unnecessary conductorization, resulting in improved stability and reduced threshold voltage variations.
Implementation Method 1
an active layer which is in contact with the reducing pattern, wherein the active layer comprises a channel portion, a first conductorization portion connected to one side of the channel portion, and a second conductorization portion connected to the other side of the channel portion
Data Source
AI summary
A thin film transistor, a fabricating method of the thin film transistor and a display device including the thin film transistor are provided, in which the thin film transistor includes a reducing pattern on a substrate, an active layer that is in contact with the reducing pattern, and a gate electrode at least partially overlapped with the active layer, wherein the active layer includes a channel portion, a first conductorization portion connected to one side of the channel portion, and a second conductorization portion connected to the other side of the channel portion, and the channel portion overlaps the gate electrode and does not overlap the reducing pattern.