TFT Scan Line Layering to Reduce LCD Parasitic Capacitance
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Solution Overview
Problem
Existing liquid crystal display devices face challenges in reducing the influence of parasitic capacitance between the lines wired to transistors, which affects the performance and efficiency of the display.
Innovation Solution
The configuration includes a first transistor of a first electrical conductivity type and a second transistor of a second electrical conductivity type, with scan lines in different layers and source-drain electrodes interposed between them, reducing parasitic capacitance through the use of pixel relay and data line relay electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If scan lines are disposed in the same plane for both N-type and P-type transistors, then the device structure is simplified and easier to manufacture, but parasitic capacitance between the scan lines increases
Solution Approach 1:
The patent applies dimensional separation by disposing the first scan line in a first layer and the second scan line in a second layer, vertically separating the N-type and P-type transistor gate lines. This multi-layer configuration reduces parasitic capacitance between scan lines while maintaining structural organization, resolving the contradiction between manufacturing simplicity and parasitic capacitance reduction.
Solution Approach 2:
The patent introduces a third scan line disposed between the first and second scan lines as an intermediary element. This third scan line acts as a buffer that further reduces parasitic capacitance coupling between the N-type and P-type transistor gate lines, while the overall multi-layer structure remains manufacturable using standard thin-film transistor fabrication processes.
2Object-affected harmful factors
If scan lines are separated into different layers to reduce parasitic capacitance, then parasitic capacitance is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent utilizes vertical layering with the first scan line in a first layer, the third scan line in a second layer, and the second scan line in a third layer. This dimensional arrangement reduces parasitic capacitance while maintaining a systematic structure that can be fabricated using conventional multi-layer thin-film transistor processes, thus managing complexity.
Solution Approach 2:
The patent applies different structural configurations to different regions: the first and second scan lines are disposed on opposite sides of the source-drain electrode, while the third scan line is positioned between them. This localized structural differentiation optimizes parasitic capacitance reduction in specific areas while maintaining overall structural coherence and manufacturability.
3Object-affected harmful factors
If the third scan line is disposed between the first and second scan lines, then parasitic capacitance is further reduced, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent implements a three-layer vertical structure where the third scan line is disposed between the first and second scan lines in the vertical dimension. This configuration maximizes parasitic capacitance reduction by introducing an intermediate buffer layer, while the overall structure remains compatible with sequential thin-film deposition and patterning processes used in standard TFT manufacturing.
Solution Approach 2:
The patent segments the scan line structure into three distinct layers (first scan line in first layer, third scan line in second layer, second scan line in third layer), allowing independent optimization of each layer's position and thickness. This segmentation enables precise control over parasitic capacitance while maintaining compatibility with modular manufacturing processes.
Data Source
AI summary
An electro-optical device includes: a first transistor of a first electrical conductivity type; a second transistor of a second electrical conductivity type; a first source-drain electrode electrically coupled to a first source-drain region of the first transistor; a second source-drain electrode electrically coupled to a second source-drain region of the second transistor; a first scan line disposed in a first layer between the first transistor and the first source-drain electrode, and electrically coupled to a first gate electrode of the first transistor; and a second scan line disposed in a second layer on a side opposite the second transistor with the second source-drain electrode interposed therebetween, and electrically coupled to a second gate electrode of the second transistor.