Thin-Film Transistor With Segmented Semiconductor Layers
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Solution Overview
Problem
Thin-film transistors (TFTs) in liquid crystal display devices experience poor electrical characteristics, leading to increased off current, decreased contrast ratio, and longer manufacturing times, which elevate costs due to the need for compensating semiconductor pattern defects.
Innovation Solution
A TFT design featuring a semiconductor pattern with layers deposited at different speeds, where the channel region forms an interface with a protective layer at a slower speed, and a gate insulation layer is used to improve electron mobility and reduce off current without increasing manufacturing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor pattern is deposited at a higher deposition speed to increase productivity, then manufacturing time is reduced, but electrical characteristics deteriorate and off current increases
Solution Approach 1:
The semiconductor pattern is divided into multiple layers (first semiconductor layer and second semiconductor layer) with different deposition speeds. The first layer is deposited at a slower speed to ensure good electrical characteristics at the interface with the protective layer, while the second layer is deposited at a faster speed to maintain productivity. This segmentation allows each layer to be optimized for its specific function.
Solution Approach 2:
Different regions of the semiconductor pattern are deposited with different qualities. The channel region (first semiconductor layer) that forms the interface with the protective layer is deposited at a slower speed to achieve superior electrical characteristics in this critical area, while other regions (second semiconductor layer) are deposited at a faster speed to maintain overall manufacturing efficiency.
2Reliability
If the semiconductor pattern is deposited at a slower deposition speed to improve electrical characteristics, then off current decreases, but manufacturing time increases
Solution Approach 1:
The semiconductor pattern is segmented into layers with different deposition speeds. Only the critical channel region (first semiconductor layer) is deposited at a slower speed to reduce off current, while the non-critical regions (second semiconductor layer) are deposited at a faster speed to minimize manufacturing time. This selective approach optimizes the trade-off between electrical characteristics and productivity.
Solution Approach 2:
The deposition speed is optimized locally for the channel region where electrical characteristics are most critical. The first semiconductor layer forming the channel is deposited at a slower speed to achieve low off current, while other parts of the semiconductor pattern are deposited at faster speeds to maintain acceptable manufacturing throughput.
3Reliability
If the protective layer is formed to cover the semiconductor pattern, then electrical characteristics are improved, but the interface quality with the semiconductor layer becomes critical
Solution Approach 1:
The first semiconductor layer that forms the interface with the protective layer is deposited at a slower speed to achieve superior local quality at this critical interface. This ensures good electrical characteristics where the protective layer contacts the semiconductor, while maintaining overall manufacturing efficiency through faster deposition of other layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances electrical characteristics by reducing off current, improving contrast ratio, and maintaining productivity, thus decreasing manufacturing costs and enhancing the TFT's performance.
Implementation Method 1
The semiconductor pattern is formed on the gate electrode, and includes a first semiconductor layer deposited at a first deposition speed and a second semiconductor layer deposited at a second deposition speed faster than the first deposition speed
Data Source
AI summary
In one embodiment, a thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, first and second electrodes and a protective layer. The semiconductor pattern is formed on the gate electrode, and includes a first semiconductor layer deposited at a first deposition speed and a second semiconductor layer deposited at a second deposition speed faster than the first deposition speed. The first and second electrodes are spaced apart from each other on the semiconductor pattern. The protective layer is formed on the semiconductor pattern to cover the first and second electrodes, and makes contact with a channel region of the first semiconductor layer to form an interface with the first semiconductor layer. Thus, electrical characteristics of the TFT may be improved.