Thin Film Transistor Semiconductor Extension Reduces Parasitic Capacitance
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Solution Overview
Problem
Existing thin film transistors in liquid crystal display devices suffer from increased parasitic capacitance due to overlapping metal layers, leading to signal delay and reduced display quality.
Innovation Solution
A thin film transistor design with a semiconductor layer extension portion that is covered by the drain electrode, reducing overlapping between metal layers and minimizing parasitic capacitance, featuring a drain electrode with a climbing portion and a flat portion, and a source electrode in a U-shaped form to enhance channel area and prevent disconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the line width of the climbing portion of the drain electrode is increased locally to reduce disconnection risk, then the reliability of the etching process is improved, but the overlapping area between the first metal layer and the second metal layer is increased, resulting in increased parasitic capacitance
Solution Approach 1:
The patent extends the semiconductor layer in the channel direction beyond the gate electrode's projection range, creating a spatial separation in the planar dimension. This allows the drain electrode's climbing portion to be positioned over the extended semiconductor layer rather than overlapping with the gate electrode, thus achieving both increased reliability (wider climbing portion) and reduced parasitic capacitance (no overlap with gate electrode).
Solution Approach 2:
The extended semiconductor layer acts as an intermediary structure that enables the drain electrode to have a wider climbing portion for reliability while preventing direct overlap between the drain electrode and gate electrode. The extension portion serves as a mediator that decouples the conflicting requirements of reliability and parasitic capacitance reduction.
2Area of stationary object
If the source electrode and drain electrode are made narrow in width, then the device area is reduced, but the risk of disconnection in the etching process is increased
Solution Approach 1:
The patent applies local quality by having the drain electrode with different widths in different regions: a narrow flat portion for normal operation and a wider climbing portion for reliable etching. This localized width variation allows the electrode to maintain small overall area while ensuring connection reliability at the critical climbing portion during fabrication.
3Ease of manufacture
If the overlapping area between the first metal layer and the second metal layer is increased, then the manufacturing robustness is improved, but the parasitic capacitance is increased, affecting display quality
Solution Approach 1:
The patent utilizes the planar dimension by extending the semiconductor layer beyond the gate electrode's projection, creating a new spatial configuration. This dimensional adjustment allows the drain electrode to be positioned such that its climbing portion overlaps with the extended semiconductor layer rather than with the gate electrode, thereby reducing parasitic capacitance while maintaining manufacturing robustness through adequate overlap area.
Data Source
AI summary
Disclosed are a thin film transistor and a display device, which can reduce parasitic capacitance between the first metal layer and the second metal layer so as to improve display quality of a liquid crystal display device. The thin film transistor includes a gate electrode, a gate insulation layer covering the gate electrode, a semiconductor layer formed on the gate insulation layer, and a source electrode and a drain electrode formed on the semiconductor layer. The semiconductor layer has an extension portion, a plane projection of which goes beyond a range of the gate electrode, and the drain electrode covers the extension portion.