TFT Semiconductor Layer Geometry for Parasitic Capacitance Control

The patent applies local quality by making the semiconductor layer extend beyond the gate electrode boundaries in specific regions. The semiconductor layer has different spatial configurations: it overlaps the gate electrode in the channel region, extends beyond the gate electrode width in overlapping regions, and contacts the drain electrode. This localized variation in semiconductor layer geometry controls the parasitic capacitance distribution, reducing display non-uniformity while maintaining standard TFT fabrication processes.

The patent transitions from a two-dimensional planar configuration where the semiconductor layer is confined within the gate electrode boundaries to a three-dimensional configuration where the semiconductor layer extends beyond the gate electrode in the overlapping region. This dimensional extension creates additional overlap area between the semiconductor layer and gate electrode, providing control over parasitic capacitance while maintaining compact TFT footprint.

The patent implements preliminary action by structuring the semiconductor layer to extend beyond the gate electrode boundaries before the display operation begins. This pre-configured semiconductor layer geometry establishes controlled parasitic capacitance characteristics across all pixels, eliminating the need for complex per-pixel image data correction. The structural design proactively prevents parasitic capacitance variation issues rather than requiring reactive software compensation.