Thin Film Transistor Semiconductor Layer Thickness Control
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Solution Overview
Problem
Low temperature polysilicon thin film transistors (TFTs) face limitations in large-sized panel fabrication due to constraints in implantation machine specifications, while amorphous silicon TFTs are suitable for large area production but have inferior carrier mobility and device stability.
Innovation Solution
A thin film transistor (TFT) structure and fabrication method where a semiconductor layer with a specific thickness range (200 Å to 800 Å) is maintained between the source and drain, allowing for superior device characteristics and enabling large area production without requiring doping machines, by forming a patterned doped semiconductor layer and using crystallization methods like solid phase crystallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low temperature polysilicon TFT fabrication is used, then device stability and carrier mobility are improved, but fabrication is limited to small-sized panels due to implantation machine specifications
Solution Approach 1:
The patent changes the fabrication approach by replacing ion implantation with chemical vapor deposition (CVD) for forming the semiconductor layer, and uses solid phase crystallization (SPC) to transform amorphous silicon to polysilicon. This parameter change in the fabrication process enables large area production while maintaining polysilicon's superior electrical properties
Solution Approach 2:
The patent substitutes the mechanical ion implantation system with a chemical deposition system (CVD) followed by thermal crystallization. This replacement eliminates the constraint of implantation machine size specifications, allowing fabrication of large-sized panels while achieving polysilicon TFT performance
2Productivity
If amorphous silicon TFT fabrication is used, then large area production is enabled, but carrier mobility and device stability deteriorate
Solution Approach 1:
The patent utilizes solid phase crystallization (SPC) to transform the semiconductor layer from amorphous phase to polysilicon phase after CVD deposition. This phase transition enables the material to achieve polysilicon's superior carrier mobility and device stability while maintaining compatibility with large area CVD fabrication processes
Solution Approach 2:
The patent performs preliminary CVD deposition of amorphous silicon layer with controlled thickness (200-800 Å) before crystallization. This preliminary action prepares the material in a state that enables subsequent complete crystallization to polysilicon, achieving high mobility while maintaining large area production capability
3Ease of manufacture
If the semiconductor layer thickness is not controlled within 200 Å to 800 Å, then fabrication flexibility is improved, but device characteristics deteriorate
Solution Approach 1:
The patent establishes an optimal thickness range (200-800 Å) for the semiconductor layer that balances fabrication flexibility with device performance. This parameter optimization allows standard CVD processes to be used while ensuring superior device characteristics after crystallization
Solution Approach 2:
The patent specifies a thickness range rather than a single value, allowing some variation (partial precision) while ensuring the layer is thin enough for complete crystallization but thick enough for good electrical properties. This approach maintains device characteristics without requiring excessive precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TFT achieves superior device characteristics and supports large area production, enhancing display quality by maintaining the semiconductor layer's thickness between the source and drain within the specified range, thus overcoming the limitations of existing technologies.
Implementation Method 1
crystallized parts of the polysilicon TFTs are formed by crystallization methods such as the solid phase crystallization (SPC)
Implementation Method 2
A gate insulation layer is disposed on the source, the drain and the semiconductor layer
Data Source
AI summary
A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 Å to 800 Å. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer.