Thin Film Transistor Circuit Layout with Shared Source Drain Regions
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Solution Overview
Problem
Conventional thin-film transistor (TFT) circuits face challenges with low mobility and large area requirements due to limitations in printing resolution and registration, necessitating an improvement in transistor density to enhance computing power and economic efficiency.
Innovation Solution
The arrangement of TFTs in series or parallel configurations where source and drain regions coincide, eliminating the need for intermediary metal layers, and using conductive materials like metal oxides or doped semiconductors to reduce area and improve conductivity, while maintaining functionality in logic gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional TFT circuits are laid out with separate source and drain regions connected by metal interconnect, then the circuit functionality is maintained, but the area required for the circuit becomes large
Solution Approach 1:
The patent merges the source region of one TFT with the drain region of another TFT into a single shared region. This eliminates the need for separate metal interconnect structures between transistors, thereby reducing the overall circuit area while maintaining the necessary electrical connections and functionality.
Solution Approach 2:
The shared source/drain region serves multiple functions simultaneously: it acts as the source for one TFT and the drain for another TFT. This multi-functional design eliminates redundant structures and reduces the total area required for the circuit layout.
2Ease of manufacture
If printing techniques are used for TFT fabrication, then economic efficiencies are achieved, but the resolution and registration limitations result in large area requirements
Solution Approach 1:
By merging adjacent source and drain regions into a single printed structure, the patent reduces the number of separate printing steps and registration requirements. This approach maintains compatibility with printing fabrication methods while minimizing the area occupied by interconnect structures.
3Productivity
If transistor density is increased to improve computing power, then higher computing power is achieved, but the area required for each transistor must be reduced
Solution Approach 1:
The patent merges source and drain regions between adjacent transistors, effectively eliminating the interconnect area between them. This allows transistors to be placed closer together, increasing the transistor density and thereby improving computing power within a given area.
Data Source
AI summary
A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.