TFT Pixel Circuit Shielding for Precise Low-Power Light Emission
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Solution Overview
Problem
Display devices face challenges with high integration and power consumption due to the increasing number of thin-film transistors (TFTs) connected to each display element, necessitating improved design to enhance display quality and efficiency.
Innovation Solution
The display device incorporates a pixel circuit with a first and second thin-film transistor, each with a semiconductor layer and gate electrode, and shielding layers that overlap specific channel areas, along with capacitors and power supply voltage lines, all made from various materials to optimize electrical connections and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of TFTs electrically connected to one display element is increased to precisely control light emission, then display control precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The pixel circuit is divided into multiple functional blocks including first and second TFTs with separate gate electrodes, each responsible for specific control functions. This segmentation allows precise control of light emission while organizing complexity into manageable, functionally distinct units that can be independently optimized
Solution Approach 2:
The pixel circuit design integrates multiple control functions into a unified structure where TFTs serve dual purposes in controlling different aspects of light emission. The shared display element and coordinated gate control enable one circuit configuration to handle multiple control requirements simultaneously
2Measurement precision
If the number of TFTs electrically connected to one display element is increased to precisely control light emission, then display control precision is improved, but power consumption increases
Solution Approach 1:
The pixel circuit is divided into multiple functional blocks including first and second TFTs with separate gate electrodes, each responsible for specific control functions. This segmentation allows precise control of light emission while organizing complexity into manageable, functionally distinct units that can be independently optimized
Solution Approach 2:
The invention optimizes power consumption by controlling the operational parameters of each TFT, including gate voltage levels and switching timing. By precisely managing the electrical parameters of individual TFTs, the circuit achieves accurate display control while minimizing unnecessary power dissipation
3Use of energy by moving object
If shielding layers are added to enhance electrical connectivity and reduce power consumption, then power consumption is reduced, but device complexity increases
Solution Approach 1:
Shielding layers are introduced as intermediary structures between signal lines and sensitive circuit elements. These layers act as mediators that block electromagnetic interference and reduce parasitic coupling, thereby lowering power consumption without requiring fundamental changes to the core pixel circuit architecture
Solution Approach 2:
The shielding layers are positioned in the vertical dimension above or below existing circuit layers, adding a new spatial dimension for interference management. This approach reduces power consumption through electromagnetic shielding while maintaining the original planar circuit layout, thus limiting the increase in device complexity
Data Source
AI summary
A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.