Thin-Film Transistor Side-Slope Channel for Higher Mobility
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Solution Overview
Problem
Current thin film transistors have insufficient mobility and large size, which hinders the integration of integrated circuits on substrates and increases manufacturing costs.
Innovation Solution
The design of a thin film transistor with a first gate electrode featuring side slopes and a semiconductor layer partially located on these slopes, allowing for a smaller channel length and easier formation of single crystalline grains, reducing grain boundaries and layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional thin film transistor design is used, then the transistor can be manufactured with current processes, but the mobility is insufficient and the size is too large
Solution Approach 1:
The patent applies dimensionality change by positioning the channel on the side slope of the gate electrode rather than on a flat surface. This three-dimensional configuration allows the channel to utilize the sloped surface, achieving shorter channel length and smaller transistor area while maintaining or improving mobility through the unique side-slope geometry that enables better electric field control and single-crystalline grain formation.
Solution Approach 2:
The patent changes critical geometric parameters including channel length, gate electrode dimensions, and side slope angle. By optimizing these parameters—specifically achieving channel lengths of 0.1-1 micron and controlling the side slope angle between 45-90 degrees—the transistor achieves improved mobility and reduced size simultaneously, resolving the technical contradiction.
2Productivity
If the transistor size is reduced for better integration, then integration of circuits on substrate is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-forming the gate electrode with controlled side slopes before depositing the channel layer. This sequential process ensures that the channel, when deposited on the side slope, automatically achieves the desired length and positioning. The side slope geometry is established in advance, which guides the channel formation and reduces subsequent manufacturing variability.
Solution Approach 2:
The patent applies local quality by creating different surface geometries in different regions—the side slope region provides a controlled environment for short-channel formation, while other regions maintain conventional structures. This localized optimization allows precise channel length control in the critical area without requiring high precision across the entire transistor structure.
Data Source
AI summary
A display panel is provided by embodiments of the present application, a thin film transistor includes: a first gate electrode including a first side slope, a second side slope oppositely arranged, and a top surface; a first gate insulating layer covering the first gate electrode; a semiconductor layer arranged on the first gate insulating layer, wherein the semiconductor layer includes a first end, a second end, and a channel arranged between the first end and the second end, the second end is at least partially on the top surface, the channel is at least partially located on the first side slope.