TFT Dielectric Sidewall Recesses for Lower Parasitic Capacitance
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Solution Overview
Problem
Integrated circuits face challenges in reducing parasitic capacitance in backend structures, leading to signal delays and slower access times due to densely packed interconnects and conductive features, which complicates the formation of memory structures and requires complex patterning and etching processes.
Innovation Solution
The formation of indented or dimpled dielectric sidewall features in thin film transistor (TFT) structures within the interconnect region, which reduces parasitic capacitance by decreasing the effective area between contacts and the gate electrode, achieved through selective lateral etching and conformal deposition of a dielectric liner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interconnect structures are densely packed to reduce transistor area, then area is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating an indented region specifically at the sidewall of the semiconductor channel adjacent to the gate electrode. This localized modification reduces parasitic capacitance in the critical area where the contact approaches the gate, while maintaining the overall dense packing of the interconnect structure. The indentation creates a dielectric spacer that locally increases the distance between the contact and gate electrode, thereby reducing capacitance without requiring overall structure enlargement.
2Ease of manufacture
If conventional patterning methods are used to form sidewall features, then manufacturing is simpler, but defects increase due to multiple masks
Solution Approach 1:
The patent employs preliminary action by first forming the semiconductor channel structure with its sidewalls exposed, then using a selective etch process to create the indented region before depositing the conductive contact material. This sequence allows the indentation to be formed as a preparatory step that guides subsequent contact formation, eliminating the need for additional masking steps and reducing defect rates associated with multiple patterning operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases parasitic capacitance, improving memory performance by reducing signal delays and simplifying the patterning process, while minimizing the need for multiple masks and reducing defects during etching.
Implementation Method 1
laterally etching an exposed sidewall of the semiconductor region to form a lateral recess at the semiconductor region
Implementation Method 2
conformally depositing a dielectric liner along the sidewall
Data Source
AI summary
Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.