Thin-Film Transistor Sidewall Taper Angle Control
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Solution Overview
Problem
In the manufacturing of thin-film transistors, particularly in high-definition display devices using a Ti-based/Al-based/Ti-based laminated film as the interconnect layer, the large taper angles of sidewalls formed during etching lead to cavities in the passivation film, causing the semiconductor layer to degrade due to water or hydrogen ingress, resulting in conductivity issues.
Innovation Solution
A method involving the formation of a semiconductor layer on a gate electrode with an insulating layer, followed by patterning the interconnects and electrodes, and then patterning the semiconductor layer in an island shape, with a two-stage etching process to control taper angles of sidewalls within a range of 45 to 75 degrees, ensuring a tight coverage by the passivation film and preventing cavity formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Ti-based/Al-based/Ti-based laminated film is used as the interconnect layer to obtain high-definition display device, then the display definition is improved, but the sidewall taper angle becomes large which causes cavity formation in the passivation film
Solution Approach 1:
The etching process is divided into two distinct stages: first etching the interconnect layer to form signal lines and scanning lines, then etching the semiconductor layer to form transistor regions. This segmentation allows independent optimization of each etching step, enabling precise control of sidewall taper angles while maintaining high display definition using the Ti-based/Al-based/Ti-based laminated film structure.
2Ease of manufacture
If the sidewall taper angle is large, then the etching process is simpler, but the passivation film forms cavities that allow water and hydrogen ingress degrading the semiconductor layer
Solution Approach 1:
The patent applies preliminary protective measures by forming a carefully controlled passivation film structure before the semiconductor layer is exposed to environmental factors. The two-stage etching process is designed in advance to produce sidewall angles that ensure proper passivation film coverage, preventing future degradation from water and hydrogen ingress.
3Reliability
If the passivation film is formed to cover the sidewalls, then the semiconductor layer is protected, but the large taper angle causes cavity formation reducing coverage
Solution Approach 1:
The patent changes the critical parameter of sidewall taper angle through controlled etching conditions, optimizing it to fall within a specific range that enables complete passivation film coverage. By adjusting etching parameters to achieve appropriate sidewall angles, the passivation film can continuously cover from the bottom to the top of the sidewalls without forming cavities, ensuring reliable semiconductor layer protection.
Data Source
AI summary
According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.