TFT Manufacturing Using Simultaneous Patterning and Inert Atmosphere
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Solution Overview
Problem
The existing methods for manufacturing thin film transistors (TFTs) face issues with contamination and non-uniform characteristics due to exposure of amorphous silicon to air during crystallization and direct contact with photoresist during patterning, leading to inconsistent electron mobility and device performance.
Innovation Solution
A method involving the simultaneous formation and patterning of a buffer layer, amorphous silicon layer, and insulating layer to prevent exposure to air and direct contact with photoresist, followed by crystallization and subsequent processing steps to form a polycrystalline silicon layer and gate electrode, ensuring uniformity and reducing contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the amorphous silicon layer is exposed to air during crystallization and directly contacts photoresist during patterning, then the manufacturing process is simple and straightforward, but contamination occurs and the TFT exhibits non-uniform characteristics
Solution Approach 1:
An insulating layer is introduced as an intermediary between the amorphous silicon layer and the photoresist. This insulating layer prevents direct contact and contamination while allowing the patterning process to proceed. The insulating layer is formed by depositing silicon oxide or silicon nitride, then patterning it to create a mask that protects the silicon layer during subsequent etching operations.
Solution Approach 2:
The crystallization process is performed in an inert atmosphere (nitrogen or vacuum) rather than in air. This prevents oxidation and contamination of the amorphous silicon layer during the high-temperature crystallization process, ensuring uniform electrical characteristics and preventing degradation of the silicon layer quality.
2Device complexity
If the amorphous silicon layer is exposed to air during crystallization, then no additional protective measures are needed, but contamination occurs leading to non-uniform TFT characteristics
Solution Approach 1:
The crystallization process is performed in an inert atmosphere (nitrogen or vacuum) rather than in air. This prevents oxidation and contamination of the amorphous silicon layer during the high-temperature crystallization process, ensuring uniform electrical characteristics and preventing degradation of the silicon layer quality.
3Ease of manufacture
If the polycrystalline silicon layer directly contacts photoresist during patterning, then the patterning process is straightforward, but contamination occurs affecting TFT uniformity
Solution Approach 1:
An insulating layer is introduced as an intermediary between the amorphous silicon layer and the photoresist. This insulating layer prevents direct contact and contamination while allowing the patterning process to proceed. The insulating layer is formed by depositing silicon oxide or silicon nitride, then patterning it to create a mask that protects the silicon layer during subsequent etching operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and electrical characteristics of TFTs, improving their reliability and display quality by preventing contamination and maintaining the integrity of the amorphous silicon layer during processing.
Implementation Method 1
crystallizing the amorphous silicon layer as a polycrystalline silicon layer
Data Source
AI summary
A method of manufacturing a thin film transistor (TFT) comprises forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer. The first portion is formed on the gate insulating layer and overlaps a channel region of a semiconductor layer, and the second portion contacts the semiconductor layer. A source region and a drain region are formed on the semiconductor layer by doping a region of the semiconductor layer. The region excludes the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode. An interlayer insulating layer is formed on the gate electrode so as to cover the gate insulating layer; contact holes are formed on the interlayer insulating layer and the gate insulating layer so as to expose the source region and the drain region, and simultaneously an opening for exposing the second portion is formed. A source electrode and a drain electrode are formed by patterning a conductive layer on the interlayer insulating layer. The source electrode and the drain electrode are electrically connected to the source region and the drain region via the contact holes, and simultaneously the second portion exposed via the opening is removed.