Thin Film Transistor Single Ion Doping LDD Formation
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Solution Overview
Problem
The manufacturing process for thin film transistors, particularly those using polycrystalline silicon, is complicated and costly due to the need for multiple ion doping processes to form lightly doped drain (LDD) regions, which increases off-current and hot carrier effects.
Innovation Solution
A method that forms source and drain regions, along with high resistance regions, through a single ion doping process, simplifying the process and reducing costs by using smaller high resistance regions that block electric field increases, thereby reducing leakage current and improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ion doping processes are used to form LDD regions, then off-current is suppressed and hot carrier effects are reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the formation of LDD regions and source/drain regions into a single ion doping process by using a patterned gate electrode as a mask. This merging of multiple doping steps into one reduces manufacturing complexity while maintaining the reliability benefits of LDD structures through the self-aligned formation of lightly doped regions between the channel and heavily doped source/drain regions.
2Reliability
If multiple ion doping processes are used to form LDD regions, then hot carrier effects are suppressed, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple ion doping processes into a single process step by utilizing the patterned gate electrode as a self-aligned mask. This approach maintains the hot carrier effect suppression benefits of LDD regions while significantly reducing manufacturing cost by eliminating the need for multiple masking and doping cycles.
Solution Approach 2:
The patterned gate electrode serves a dual function: as the functional gate structure and as the masking layer for ion doping. This self-service approach eliminates the need for separate mask layers and multiple alignment processes, reducing manufacturing cost while ensuring precise formation of LDD regions for hot carrier suppression.
3Reliability
If LDD regions are formed between channel and source/drain regions, then electric field increase is prevented, but device structure becomes more complex
Solution Approach 1:
The patent combines the formation of LDD regions and source/drain regions into a single ion doping process step. The patterned gate electrode automatically defines the boundaries of LDD regions through self-alignment, creating the necessary electric field control without requiring additional structural elements or complex multi-layer configurations.
Solution Approach 2:
The gate electrode structure serves dual purposes: as the functional gate and as the masking element for doping. This self-service mechanism automatically creates the LDD region geometry needed for electric field control, simplifying the overall device structure compared to approaches requiring separate mask layers and alignment structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity and costs while enhancing the reliability of thin film transistors by minimizing leakage current and hot carrier effects, achieved through the use of high resistance regions that function similarly to LDD regions without the need for multiple doping masks.
Implementation Method 1
An ion doping process is performed using the etching mask disposed on the gate electrode 140 as an ion implantation mask to form lightly doped drain (LDD) regions 122
Data Source
AI summary
A thin film transistor, a method of fabricating the same, and a flat panel display device including the same, are provided. According to the method, low resistance regions and high resistance regions can be manufactured through one doping process. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including source and drain regions, high resistance regions smaller than the source and drain regions, a channel region, and connection regions disposed between the high resistance regions and the channel region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer above the channel region; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions, respectively.