TFT Array Substrate Single-Mask Patterning for Cost Reduction
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Solution Overview
Problem
The high manufacturing costs and complexity associated with preparing multiple masks for photolithography processes in producing thin-film transistor (TFT) array substrates for flat panel displays, which increases the overall cost and time required for manufacturing.
Innovation Solution
A method of manufacturing TFT array substrates where a non-doping semiconductor layer is formed on the entire substrate without a separate patterning process using masks, reducing the number of masks needed and simplifying the process, allowing for the simultaneous formation of TFTs and capacitors with reduced manufacturing costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used in photolithography processes to form TFT patterns, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple photolithography processes that previously required separate masks into a single process using one mask. The mask simultaneously defines the active layer pattern, gate electrode pattern, and source/drain electrode patterns through strategic positioning and overlapping exposure areas, thereby reducing mask preparation complexity while maintaining manufacturing precision
Solution Approach 2:
The single mask serves multiple functions by being used to pattern different components (active layer, gate electrode, source/drain electrodes) in sequence during the same photolithography process. This multi-functional approach eliminates the need for separate masks for each component, reducing overall device complexity and manufacturing cost
2Manufacturing precision
If multiple masks are prepared for photolithography processes, then TFT pattern quality is improved, but manufacturing time increases
Solution Approach 1:
Multiple photolithography steps that previously required sequential mask preparation and alignment are merged into a single exposure process. The mask is positioned and exposed multiple times on the same substrate during one continuous process flow, eliminating the time required to prepare, align, and exchange multiple masks while maintaining TFT pattern quality through consistent exposure parameters
3Manufacturing precision
If multiple masks are used in the manufacturing process, then capacitor and TFT pattern precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the patterning processes for capacitors and TFTs into a single photolithography step using one mask. The mask design allows simultaneous definition of capacitor electrodes and TFT components through overlapping exposure regions, reducing the number of masks required and thereby lowering manufacturing cost while maintaining the precision needed for both capacitor and TFT patterns
Solution Approach 2:
The single mask is designed to serve multiple patterning functions for both capacitor and TFT fabrication. By strategically positioning mask features and controlling exposure parameters, the same mask enables precise pattern formation for different device types, eliminating the need for separate masks and reducing overall manufacturing cost
Data Source
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Figure 3A~3B
AI summary
A thin-film transistor (TFT) array substrate including at least one TFT, the at least one TFT including a semiconductor layer including a source region and a drain region having a first doping concentration on a substrate, a channel region between the source and drain regions and having a second doping concentration, the second doping concentration being lower than the first doping concentration, and a non-doping region extending from the source and drain regions; a gate insulating layer on the semiconductor layer; a gate electrode on the gate insulating layer and at least partially overlapping the channel region; and a source electrode and a drain electrode insulated from the gate electrode and electrically connected to the source region and the drain region, respectively.