Thin-Film Transistor Source-Drain Thickness Control
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Solution Overview
Problem
Conventional methods for fabricating Thin-Film Transistors (TFTs) in LCD devices require a high number of process steps, leading to increased fabrication costs and potential degradation of TFT characteristics due to heavy-metal impurity diffusion, while also compromising alignment accuracy.
Innovation Solution
A semiconductor device with a TFT structure where the source/drain regions are thinner than the remainder of the semiconductor film by a controlled thickness difference (10-100 angstroms), allowing for selective removal of heavy-metal impurities and simultaneous crystallization and activation of impurities using excimer laser annealing, along with improved alignment marks placement for higher accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional multi-step fabrication process is used, then alignment marks can be formed, but the number of process steps increases and fabrication cost becomes high
Solution Approach 1:
The invention combines the formation of alignment marks and source/drain regions into a single ion implantation step using a unified mask pattern. This merging of processes reduces the total number of fabrication steps while maintaining alignment accuracy, directly resolving the contradiction between process complexity and measurement precision.
Solution Approach 2:
The mask pattern serves multiple functions simultaneously: it defines both the alignment marks and the source/drain regions, and the ion implantation process achieves both marker formation and doping in one step. This multi-functionality eliminates redundant process steps while preserving alignment capabilities.
2Reliability
If ion implantation is performed for source/drain region formation, then doping is achieved, but heavy-metal impurity diffusion degrades TFT characteristics
Solution Approach 1:
The invention extracts and removes heavy-metal impurities from the semiconductor film through selective etching of the source/drain regions after ion implantation. This extraction process eliminates the harmful impurity diffusion that would otherwise degrade TFT characteristics, while preserving the beneficial doping effects.
Solution Approach 2:
The ion implantation process, which initially introduces heavy-metal impurities as a harmful effect, is converted into a beneficial process by subsequently removing only the impurities while retaining the doped source/drain regions. The harmful impurity diffusion is transformed into a controllable step that ultimately improves TFT characteristics.
3Manufacturing precision
If multiple mask formation steps are used, then precise patterning is achieved, but fabrication cost increases
Solution Approach 1:
The invention merges multiple mask formation and patterning steps into a single mask creation and ion implantation process. By defining both alignment marks and source/drain regions in one masking step, the process reduces fabrication cost while maintaining pattern alignment precision through the unified approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of fabrication steps, enhances alignment accuracy, and improves the reliability and operation characteristics of TFTs by preventing heavy-metal impurity diffusion, thereby lowering costs and maintaining high performance.
Implementation Method 1
the a-Si film thus formed is subjected to a selective exposure process and a development process, thereby forming a first mask with a pattern for first alignment marks
Implementation Method 2
the a-Si film (wherein the first alignment marks have been formed) is crystallized by the solid-phase growth, the excimer laser annealing, or the like, resulting in a polycrystalline silicon film
Implementation Method 3
impurity or dopant ions are selectively implanted into source/drain formation regions (which are regions to be formed as source/drain regions later and which may be termed S/D formation regions below) of the island-shaped polysilicon film
Implementation Method 4
a first photosensitive resist film is formed on the a-Si film, and the a-Si film thus formed is subjected to a selective exposure process and a development process, thereby forming a first mask with a pattern for first alignment marks
Data Source
AI summary
A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor film. The pair of source/drain regions is thinner than the remainder of the semiconductor film other than the source/drain regions. The thickness difference between the pair of source/drain regions and the remainder of the semiconductor film is in a range from 10 angstrom (Å) to 100 angstrom. The total process steps are reduced and the operation characteristic and reliability of the device are improved.