Thin-Film Transistor Spacer-Controlled Gate Length for Current Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Thin-film transistors (TFTs) fabricated using bottom gate technologies exhibit variations in gate length due to lithography technology and edge roughness, affecting on and off currents, which impacts the performance and retention time of memory cells in memory arrays.
Innovation Solution
The gate length of TFTs is determined by a spacer, with the spacer overlapping the gate electrode, allowing for shorter gate lengths than the pitch between source and drain electrodes, reducing current variations and improving performance and retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate length is determined by lithography pitch between source and drain electrodes, then the fabrication process is simplified, but the gate length varies due to edge roughness and pitch variations, adversely affecting on and off currents
Solution Approach 1:
The patent introduces a spacer as an intermediary element that determines the gate length, decoupling the gate length from the lithography pitch between source and drain electrodes. The spacer acts as a mediator that defines the gate electrode length through its width, which can be controlled with higher precision than lithography pitch, thereby reducing gate length variations while maintaining fabrication simplicity
Solution Approach 2:
The spacer is formed before the gate electrode patterning step, preliminarily defining the gate length. This preliminary action allows the gate electrode to be patterned with precise length control based on the spacer width, rather than relying on subsequent lithography steps that are subject to pitch and edge roughness variations
2Reliability
If the gate length is reduced to improve transistor performance, then on and off currents are improved, but the gate length becomes more sensitive to variations from lithography and edge roughness
Solution Approach 1:
The spacer serves as a precision template that mediates the relationship between lithography and the final gate length. By using the spacer width (which can be precisely controlled) as the reference for gate length rather than directly relying on lithography pitch, the method enables reduced gate lengths with improved control and reduced sensitivity to lithography variations
3Productivity
If the pitch between source and drain electrodes is reduced to increase device density, then more devices can be integrated, but the gate length determined by this pitch becomes smaller and more variable
Solution Approach 1:
The patent shifts the gate length determination from the lateral dimension (lithography pitch between source and drain) to a different dimensional approach using the spacer width. This allows the pitch between source and drain electrodes to be reduced for higher density while the gate length is controlled by the spacer dimension, which can be independently optimized for uniformity
Solution Approach 2:
The spacer acts as an intermediary that decouples the gate length from the source-drain pitch. This allows the pitch to be reduced for higher density while the spacer maintains consistent gate length across devices, resolving the trade-off between density and uniformity
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.