Thin-Film Transistor Stacked Active Layers Aperture Ratio
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing thin-film transistors in OLED display apparatuses require larger active layers to achieve higher on-state current, which increases the thickness and affects the aperture ratio of the display apparatus.
Innovation Solution
A thin-film transistor design featuring a first active layer, source, drain, and gate with a second active layer on top, where the gate is insulated from both active layers, allowing for increased current flow without expanding the active layer area, and an insulating layer wrapping the gate to prevent parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the area of the active layer is increased to obtain a larger on-state current, then the on-state current is improved, but the aperture ratio of the display apparatus deteriorates
Solution Approach 1:
The patent introduces a vertical stacking dimension by placing a second active layer above the first active layer, transforming the traditional planar structure into a three-dimensional stacked structure. This allows the transistor to achieve higher on-state current through increased vertical conduction paths without expanding the horizontal area occupied by the active layer, thereby maintaining the aperture ratio while improving current capability.
Solution Approach 2:
The patent implements a nested structure where the second active layer is positioned above the first active layer, and both layers are integrated within the same horizontal footprint. The gate electrode and insulating layers are also nested vertically, creating a compact stacked configuration that maximizes current flow paths within a limited area, resolving the contradiction between current magnitude and area occupation.
2Power
If the area of the active layer is increased to obtain a larger on-state current, then the on-state current is improved, but the thickness of the display apparatus increases
Solution Approach 1:
The patent utilizes the vertical dimension efficiently by stacking active layers and other components (gate, insulating layers) in a compact arrangement. This vertical integration allows the transistor to achieve enhanced current capability through multiple conduction paths without requiring a proportional increase in overall device thickness, as the stacked structure optimizes space utilization in the vertical direction.
3Power
If a second active layer is added on top of the gate and source/drain, then the on-state current is enhanced, but the device complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct functional layers: a first active layer for carrier injection, a gate electrode for control, insulating layers for electrical isolation, and a second active layer for current conduction. This segmentation allows each component to be optimized independently and simplifies the manufacturing process by enabling sequential deposition and patterning of each layer, thereby managing complexity through modular design.
Solution Approach 2:
The second active layer serves multiple functions: it provides additional current conduction paths to enhance on-state current, maintains electrical isolation from the gate through the insulating layer, and integrates with the source and drain electrodes to form complete current pathways. This multi-functionality reduces the need for additional specialized components, thereby controlling overall device complexity while achieving current enhancement.
Data Source
AI summary
A thin-film transistor, method of manufacturing the same, and a display apparatus are provided. The thin-film transistor includes a first active layer, a source, a drain, a gate, and a second active layer, the source, the drain, the gate are disposed on the first active layer with spacing, the gate is located between the source and the drain, the second active layer is disposed on the gate, the source, and the drain, the source and the drain are both respectively connected to the first active layer and the second active layer, and the gate is respectively insulated from the first active layer, the second active layer, the source, and the drain. When a voltage is applied to the gate, the source and the drain may be conducting via the first and second active layer. Therefore, a larger current may flow between the source and the drain.