TFT Array Substrate Stacked Capacitor Aperture Ratio
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Solution Overview
Problem
In LCDs, increasing the capacitance of the storage capacitor in TFT array substrates is challenging due to the minimum threshold thickness of the gate insulating layer, which limits the reduction of the distance between capacitor electrodes, and increasing the electrode area reduces the aperture ratio, thereby diminishing display quality.
Innovation Solution
A method for manufacturing a TFT array substrate involves forming a passivation layer between the capacitor and pixel electrodes, allowing the distance between them to be reduced independently of the electrode area, thereby maintaining a high aperture ratio while enhancing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between capacitor electrodes is reduced to increase capacitance, then the capacitance increases, but the gate insulating layer thickness cannot be reduced below a minimum threshold
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by forming the second capacitor electrode on top of the first capacitor electrode through multiple photolithographic processes. This vertical stacking increases capacitance by utilizing the third dimension (height) rather than reducing the horizontal distance between electrodes, thereby avoiding the minimum thickness constraint of the gate insulating layer.
2Quantity of substance
If the electrode area is increased to increase capacitance, then the capacitance increases, but the aperture ratio decreases and display quality deteriorates
Solution Approach 1:
The stacked capacitor structure allows capacitance to be increased through vertical layering rather than horizontal expansion. The first and second capacitor electrodes are formed in different layers with overlapping areas, increasing the effective capacitance area without occupying additional pixel area, thus maintaining the aperture ratio and display quality.
Solution Approach 2:
The patent implements a nested capacitor structure where the second capacitor electrode is formed on top of the first capacitor electrode, with both electrodes having overlapping projected areas. This nesting arrangement maximizes the capacitance within the available pixel area by utilizing vertical space, preventing the need to expand electrode areas horizontally which would reduce the aperture ratio.
3Quantity of substance
If multiple photolithographic processes are used to form stacked capacitor electrodes, then the capacitance increases with adjustable thickness, but the manufacturing process complexity increases
Solution Approach 1:
The capacitor formation process is segmented into multiple photolithographic steps, with each step forming a specific layer or pattern. The first photolithographic process forms the gate electrode and first capacitor electrode, while the second photolithographic process forms the second capacitor electrode. This segmentation allows precise control over each layer's dimensions and thickness, enabling adjustable capacitance while maintaining manufacturing feasibility through standardized process modules.
Data Source
AI summary
An exemplary method for manufacturing a TFT array substrate (20) typically for use in a liquid crystal display (LCD) includes: providing an insulating substrate (30) comprising a TFT area (31), a display area (32) and a capacitor area (33); forming a gate electrode (232) at the TFT area and a capacitor electrode (222) at the capacitor area; forming an insulating layer (203), an amorphous silicon layer (204), and a doped amorphous silicon layer (205) in turn on the insulating substrate; etching the doped amorphous silicon, the amorphous silicon and the insulating layer at the display area and the capacitor area; forming a source electrode (231) and a drain electrode (233) at the TFT area; forming a passivation layer (225) at the capacitor area; and forming a pixel electrode (221) on the substrate, the pixel electrode covering the display area, the capacitor area, and part of the TFT area.